The event queue producer path wrote entries through address_space_memory with MEMTXATTRS_UNSPECIFIED, so produced entries did not use the sec_sid-selected DMA context. Pass AddressSpace and MemTxAttrs to queue_write() based on sec_sid.
Signed-off-by: Tao Tang <[email protected]> Reviewed-by: Eric Auger <[email protected]> Reviewed-by: Pierrick Bouvier <[email protected]> --- hw/arm/smmuv3.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index fa13191fc3b..7e08b88689f 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -129,7 +129,8 @@ static inline MemTxResult queue_read(SMMUQueue *q, Cmd *cmd, return ret; } -static MemTxResult queue_write(SMMUQueue *q, Evt *evt_in) +static MemTxResult queue_write(SMMUQueue *q, Evt *evt_in, + AddressSpace *as, MemTxAttrs attrs) { dma_addr_t addr = Q_PROD_ENTRY(q); MemTxResult ret; @@ -139,8 +140,7 @@ static MemTxResult queue_write(SMMUQueue *q, Evt *evt_in) for (i = 0; i < ARRAY_SIZE(evt.word); i++) { cpu_to_le32s(&evt.word[i]); } - ret = dma_memory_write(&address_space_memory, addr, &evt, sizeof(Evt), - MEMTXATTRS_UNSPECIFIED); + ret = dma_memory_write(as, addr, &evt, sizeof(Evt), attrs); if (ret != MEMTX_OK) { return ret; } @@ -155,6 +155,9 @@ static MemTxResult smmuv3_write_eventq(SMMUv3State *s, SMMUSecSID sec_sid, SMMUv3RegBank *bank = smmuv3_bank(s, sec_sid); SMMUQueue *q = &bank->eventq; MemTxResult r; + SMMUState *bs = ARM_SMMU(s); + MemTxAttrs txattrs = smmu_get_txattrs(sec_sid); + AddressSpace *as = smmu_get_address_space(bs, sec_sid); if (!smmuv3_eventq_enabled(s, sec_sid)) { return MEMTX_ERROR; @@ -164,7 +167,7 @@ static MemTxResult smmuv3_write_eventq(SMMUv3State *s, SMMUSecSID sec_sid, return MEMTX_ERROR; } - r = queue_write(q, evt); + r = queue_write(q, evt, as, txattrs); if (r != MEMTX_OK) { return r; } -- 2.34.1
