test_interrupts also now passes in full following the iassign{r,w}
fix, so enable it alongside the other arch tests.Signed-off-by: Brian Cain <[email protected]> --- tests/functional/hexagon/test_arch_tests.py | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/tests/functional/hexagon/test_arch_tests.py b/tests/functional/hexagon/test_arch_tests.py index 0834398c3b1..8e71386c186 100755 --- a/tests/functional/hexagon/test_arch_tests.py +++ b/tests/functional/hexagon/test_arch_tests.py @@ -21,8 +21,8 @@ class ArchTestsUart(QemuSystemTest): ASSET_TARBALL = Asset( "https://github.com/qualcomm/qemu-hexagon-testing/releases/"; - "download/v0.2.5/arch_tests_uart.tar.gz", - "edb4f37b877a3a72a0e10920477458a43b40045d34398fee8cb763fefd342f4f", + "download/v0.2.12/arch_tests_uart.tar.gz", + "871a339bf78cac0ebaf1b2509bfcd5b249ad8190be33e0cf848283b2f6915323", ) def run_uart_test(self, test_name: str, @@ -58,6 +58,10 @@ def test_int_steering(self) -> None: """ self.run_uart_test("test_int_steering") + def test_interrupts(self) -> None: + """Tests interrupt delivery.""" + self.run_uart_test("test_interrupts") + def test_cache(self) -> None: """Tests cache operations: dckill/ickill, l2kill, dczeroa, dccleaninva, cache disable/enable, barriers, and dcinva/dccleana. @@ -70,6 +74,10 @@ def test_l2vic(self) -> None: """ self.run_uart_test("test_l2vic") + def test_sys_regs(self) -> None: + """Tests system registers.""" + self.run_uart_test("test_sys_regs") + def test_threads(self) -> None: """Tests hardware thread management: start/stop, MODECTL state, per-thread HTID, shared memory, wait/resume, STID priority, and -- 2.34.1
