Since we're also passing env, v0 is always env->vreg.
Signed-off-by: Richard Henderson <[email protected]>
---
target/riscv/helper.h | 16 ++++++++--------
target/riscv/tcg/vector_helper.c | 4 ++--
target/riscv/tcg/insn_trans/trans_rvv.c.inc | 16 +++++-----------
3 files changed, 15 insertions(+), 21 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 8a42a6ce03..3ef352898b 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -179,14 +179,14 @@ DEF_HELPER_4(vse32_v_mask, void, ptr, tl, env, i32)
DEF_HELPER_4(vse64_v_mask, void, ptr, tl, env, i32)
DEF_HELPER_4(vlm_v, void, ptr, tl, env, i32)
DEF_HELPER_4(vsm_v, void, ptr, tl, env, i32)
-DEF_HELPER_6(vlse8_v, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlse16_v, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlse32_v, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlse64_v, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vsse8_v, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vsse16_v, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vsse32_v, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vsse64_v, void, ptr, ptr, tl, tl, env, i32)
+DEF_HELPER_5(vlse8_v, void, ptr, tl, tl, env, i32)
+DEF_HELPER_5(vlse16_v, void, ptr, tl, tl, env, i32)
+DEF_HELPER_5(vlse32_v, void, ptr, tl, tl, env, i32)
+DEF_HELPER_5(vlse64_v, void, ptr, tl, tl, env, i32)
+DEF_HELPER_5(vsse8_v, void, ptr, tl, tl, env, i32)
+DEF_HELPER_5(vsse16_v, void, ptr, tl, tl, env, i32)
+DEF_HELPER_5(vsse32_v, void, ptr, tl, tl, env, i32)
+DEF_HELPER_5(vsse64_v, void, ptr, tl, tl, env, i32)
DEF_HELPER_6(vlxei8_8_v, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vlxei8_16_v, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vlxei8_32_v, void, ptr, ptr, tl, ptr, env, i32)
diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
index 66a5f68de8..15c1281538 100644
--- a/target/riscv/tcg/vector_helper.c
+++ b/target/riscv/tcg/vector_helper.c
@@ -305,7 +305,7 @@ vext_ldst_stride(void *vd, target_ulong base, target_ulong
stride,
}
#define GEN_VEXT_LD_STRIDE(NAME, ETYPE, LOAD_FN) \
-QEMU_FLATTEN void HELPER(NAME)(void *vd, void * v0, target_ulong base, \
+QEMU_FLATTEN void HELPER(NAME)(void *vd, target_ulong base, \
target_ulong stride, CPURISCVState *env, \
uint32_t desc) \
{ \
@@ -320,7 +320,7 @@ GEN_VEXT_LD_STRIDE(vlse32_v, int32_t, lde_w_tlb)
GEN_VEXT_LD_STRIDE(vlse64_v, int64_t, lde_d_tlb)
#define GEN_VEXT_ST_STRIDE(NAME, ETYPE, STORE_FN) \
-QEMU_FLATTEN void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
+QEMU_FLATTEN void HELPER(NAME)(void *vd, target_ulong base, \
target_ulong stride, CPURISCVState *env, \
uint32_t desc) \
{ \
diff --git a/target/riscv/tcg/insn_trans/trans_rvv.c.inc
b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
index 3d32564660..5e352dbf41 100644
--- a/target/riscv/tcg/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/tcg/insn_trans/trans_rvv.c.inc
@@ -878,32 +878,26 @@ GEN_VEXT_TRANS(vsm_v, MO_8, vsm_v, st_us_mask_op,
st_us_mask_check)
/*
*** stride load and store
*/
-typedef void gen_helper_ldst_stride(TCGv_ptr, TCGv_ptr, TCGv,
- TCGv, TCGv_env, TCGv_i32);
+typedef void gen_helper_ldst_stride(TCGv_ptr, TCGv, TCGv, TCGv_env, TCGv_i32);
static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
uint32_t data, gen_helper_ldst_stride *fn,
DisasContext *s)
{
- TCGv_ptr dest, mask;
- TCGv base, stride;
+ TCGv_ptr dest = tcg_temp_new_ptr();
+ TCGv base = get_gpr(s, rs1, EXT_NONE);
+ TCGv stride = get_gpr(s, rs2, EXT_NONE);
TCGv_i32 desc;
- dest = tcg_temp_new_ptr();
- mask = tcg_temp_new_ptr();
- base = get_gpr(s, rs1, EXT_NONE);
- stride = get_gpr(s, rs2, EXT_NONE);
-
data = vdata_add_memopidx(s, data);
desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,
s->cfg_ptr->vlenb, data));
tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
- tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
mark_vs_dirty(s);
- fn(dest, mask, base, stride, tcg_env, desc);
+ fn(dest, base, stride, tcg_env, desc);
finalize_rvv_inst(s);
return true;
--
2.43.0
