On Mon, Aug 10, 2026 at 04:29:56PM +0800, Tina Zhang wrote: > Date: Mon, 10 Aug 2026 16:29:56 +0800 > From: Tina Zhang <[email protected]> > Subject: [PATCH v2 9/9] target/i386: Use AMD ucode-rev default for Hygon > X-Mailer: git-send-email 2.43.7 > > QEMU currently gives named Hygon Dhyana CPUs the non-AMD default > ucode-rev value, 0x100000000. That is the Intel/KVM-VMX-shaped > encoding, where the visible revision is in the high 32 bits. > > Linux reads MSR 0x8b for Hygon CPUs through the AMD patch-level path, > using MSR_AMD64_PATCH_LEVEL and storing the low 32 bits as > cpuinfo_x86.microcode. With the old QEMU default, a Dhyana guest sees > microcode revision 0. > > Use the AMD/KVM-SVM-shaped default, 0x01000065, for Hygon on this > specific MSR 0x8b default path. This does not route Hygon through AMD > microcode loading and does not claim that Hygon CPUs are otherwise > identical to AMD CPUs. > > Preserve migration ABI through the vendor CPU ABI compatibility gate used > by this Hygon bug-fix group. pc-11.0 and older machine types leave that > gate off, so they retain the previous ucode-rev default. Explicit > user-provided ucode-rev values still override the default. > > Add qtest coverage for the new default, the compatibility cases, and an > explicit user override. > > Signed-off-by: Tina Zhang <[email protected]> > --- > target/i386/cpu.c | 8 ++++++-- > tests/qtest/test-x86-cpuid-compat.c | 19 +++++++++++++++++++ > 2 files changed, 25 insertions(+), 2 deletions(-) > > + * Hygon uses the AMD patch-level MSR 0x8b encoding, where the > visible > + * microcode revision is in the low 32 bits.
I feel like this description is redundant regarding the commit message is already self-explanatory. Adding one for each vendor might clutter the comments. Others, LGTM, Reviewed-by: Zhao Liu <[email protected]>
