gen_load_locked4u() and gen_load_locked8u() read guest memory with an explicit MO_LE, but gen_store_conditional4() and gen_store_conditional8() are missing that, so we wrongly access guest memory in host byte order.
Signed-off-by: Matheus Tavares Bernardino <[email protected]> --- target/hexagon/genptr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index 2a98b13b71..9330732c99 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -576,7 +576,7 @@ static inline void gen_store_conditional4(DisasContext *ctx, zero = tcg_constant_tl(0); tmp = tcg_temp_new(); tcg_gen_atomic_cmpxchg_tl(tmp, hex_llsc_addr, hex_llsc_val, src, - ctx->mem_idx, MO_32 | MO_ALIGN); + ctx->mem_idx, MO_LE | MO_32 | MO_ALIGN); tcg_gen_movcond_tl(TCG_COND_EQ, pred, tmp, hex_llsc_val, one, zero); tcg_gen_br(done); @@ -601,7 +601,7 @@ static inline void gen_store_conditional8(DisasContext *ctx, zero = tcg_constant_i64(0); tmp = tcg_temp_new_i64(); tcg_gen_atomic_cmpxchg_i64(tmp, hex_llsc_addr, hex_llsc_val_i64, src, - ctx->mem_idx, MO_64 | MO_ALIGN); + ctx->mem_idx, MO_LE | MO_64 | MO_ALIGN); tcg_gen_movcond_i64(TCG_COND_EQ, tmp, tmp, hex_llsc_val_i64, one, zero); tcg_gen_extrl_i64_i32(pred, tmp); -- 2.37.2
