From: Isaku Yamahata <[email protected]> CR4.LASS[bit 27] enables Linear Address Space Separation, and may be set only when CPUID.(EAX=7,ECX=1):EAX[6] enumerates LASS.
Recognize CR4.LASS as a valid bit by adding CR4_LASS_MASK to the known bits, i.e. clearing it from CR4_RESERVED_MASK. Mark it reserved in cr4_reserved_bits() and clear it in cpu_x86_update_cr4() when the guest CPUID does not enumerate LASS. This keeps CR4 handling consistent on paths that reach cpu_x86_update_cr4(), such as gdbstub register writes. LASS is not emulated by TCG, so it is not added to TCG_7_1_EAX_FEATURES and cannot be set under TCG (helper_write_crN() and helper_vmrun() both reject reserved bits via cr4_reserved_bits()). Signed-off-by: Isaku Yamahata <[email protected]> [kishen: rewrote commit message, rebased, fixed formatting] Signed-off-by: Kishen Maloor <[email protected]> --- target/i386/cpu.h | 7 ++++++- target/i386/helper.c | 4 ++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index e6a197602d..98c406db32 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -277,6 +277,7 @@ typedef enum X86Seg { #define CR4_PKE_MASK (1U << 22) #define CR4_CET_MASK (1U << 23) #define CR4_PKS_MASK (1U << 24) +#define CR4_LASS_MASK (1U << 27) #define CR4_LAM_SUP_MASK (1U << 28) #ifdef TARGET_X86_64 @@ -293,7 +294,8 @@ typedef enum X86Seg { | CR4_LA57_MASK \ | CR4_FSGSBASE_MASK | CR4_PCIDE_MASK | CR4_OSXSAVE_MASK \ | CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_PKE_MASK | CR4_CET_MASK \ - | CR4_PKS_MASK | CR4_LAM_SUP_MASK | CR4_FRED_MASK)) + | CR4_PKS_MASK | CR4_LASS_MASK | CR4_LAM_SUP_MASK \ + | CR4_FRED_MASK)) #define DR6_BD (1 << 13) #define DR6_BS (1 << 14) @@ -3064,6 +3066,9 @@ static inline uint64_t cr4_reserved_bits(CPUX86State *env) if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKS)) { reserved_bits |= CR4_PKS_MASK; } + if (!(env->features[FEAT_7_1_EAX] & CPUID_7_1_EAX_LASS)) { + reserved_bits |= CR4_LASS_MASK; + } if (!(env->features[FEAT_7_1_EAX] & CPUID_7_1_EAX_LAM)) { reserved_bits |= CR4_LAM_SUP_MASK; } diff --git a/target/i386/helper.c b/target/i386/helper.c index 6836214162..43cfcfdafe 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -229,6 +229,10 @@ void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4) new_cr4 &= ~CR4_PKS_MASK; } + if (!(env->features[FEAT_7_1_EAX] & CPUID_7_1_EAX_LASS)) { + new_cr4 &= ~CR4_LASS_MASK; + } + if (!(env->features[FEAT_7_1_EAX] & CPUID_7_1_EAX_LAM)) { new_cr4 &= ~CR4_LAM_SUP_MASK; } -- 2.47.1
