Add QEMU feature names and masks for the SM2, CCS, RNG2, PHE2 and RSA feature pairs in CPUID 0xC0000001 EDX. The matching KVM support exposes these bits through KVM_GET_SUPPORTED_CPUID.
TCG does not currently implement these instructions. Keep TCG_EXT4_FEATURES at zero so QEMU filters the bits from realized TCG CPUs. Link: https://lore.kernel.org/all/[email protected]/ Signed-off-by: Ewan Hai <[email protected]> --- target/i386/cpu.c | 10 +++++----- target/i386/cpu.h | 20 ++++++++++++++++++++ 2 files changed, 25 insertions(+), 5 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 5408d851d1..1107d1243c 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1120,14 +1120,14 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = { [FEAT_C000_0001_EDX] = { .type = CPUID_FEATURE_WORD, .feat_names = { - NULL, NULL, "xstore", "xstore-en", - NULL, NULL, "xcrypt", "xcrypt-en", + "sm2", "sm2-en", "xstore", "xstore-en", + "ccs", "ccs-en", "xcrypt", "xcrypt-en", "ace2", "ace2-en", "phe", "phe-en", "pmm", "pmm-en", NULL, NULL, NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, + NULL, NULL, "rng2", "rng2-en", + NULL, "phe2", "phe2-en", "rsa", + "rsa-en", NULL, NULL, NULL, }, .cpuid = { .eax = 0xC0000001, .reg = R_EDX, }, .tcg_features = TCG_EXT4_FEATURES, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 641f3ee5c2..60327688f4 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1243,10 +1243,18 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w); /* CPUID[0x80000007].EDX flags: */ #define CPUID_APM_INVTSC (1U << 8) +/* SM2 algorithm */ +#define CPUID_C000_0001_EDX_SM2 (1U << 0) +/* SM2 enabled */ +#define CPUID_C000_0001_EDX_SM2_EN (1U << 1) /* "rng" RNG present (xstore) */ #define CPUID_C000_0001_EDX_XSTORE (1U << 2) /* "rng_en" RNG enabled */ #define CPUID_C000_0001_EDX_XSTORE_EN (1U << 3) +/* SM3 and SM4 algorithms */ +#define CPUID_C000_0001_EDX_CCS (1U << 4) +/* CCS enabled */ +#define CPUID_C000_0001_EDX_CCS_EN (1U << 5) /* "ace" on-CPU crypto (xcrypt) */ #define CPUID_C000_0001_EDX_XCRYPT (1U << 6) /* "ace_en" on-CPU crypto enabled */ @@ -1263,6 +1271,18 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w); #define CPUID_C000_0001_EDX_PMM (1U << 12) /* PMM enabled */ #define CPUID_C000_0001_EDX_PMM_EN (1U << 13) +/* Random Number Generator v2 */ +#define CPUID_C000_0001_EDX_RNG2 (1U << 22) +/* RNG2 enabled */ +#define CPUID_C000_0001_EDX_RNG2_EN (1U << 23) +/* PadLock Hash Engine v2 */ +#define CPUID_C000_0001_EDX_PHE2 (1U << 25) +/* PHE2 enabled */ +#define CPUID_C000_0001_EDX_PHE2_EN (1U << 26) +/* Big-number arithmetic */ +#define CPUID_C000_0001_EDX_RSA (1U << 27) +/* RSA enabled */ +#define CPUID_C000_0001_EDX_RSA_EN (1U << 28) #define CPUID_VENDOR_SZ 12 #define CPUID_MODEL_ID_SZ 48 -- 2.34.1
