On 2026/08/26 10:38 AM, Chinmay Rath wrote: > From: Ojaswin Mujoo <[email protected]> > > Moving the following instructions to decodetree specification : > isync > > The changes were verified by validating that the tcg ops generated by > those instructions remain the same, which were captured with the '-d > in_asm,op' flag.
Nit: Trailing period in subject line. Otherwise, Reviewed-by: Amit Machhiwal <[email protected]> > > Signed-off-by: Ojaswin Mujoo <[email protected]> > Reviewed-by: Nikhil Kumar Singh <[email protected]> > Reviewed-by: Glenn Miles <[email protected]> > Signed-off-by: Chinmay Rath <[email protected]> > --- > target/ppc/insn32.decode | 1 + > target/ppc/translate.c | 15 --------------- > target/ppc/translate/storage-ctrl-impl.c.inc | 17 +++++++++++++++++ > 3 files changed, 18 insertions(+), 15 deletions(-) > > diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode > index a1c2f549bd..91ece88a70 100644 > --- a/target/ppc/insn32.decode > +++ b/target/ppc/insn32.decode > @@ -1472,6 +1472,7 @@ MSGSYNC 011111 ----- ----- ----- 1101110110 - > @X_sync ...... .. l:3 ... sc:2 ..... .......... . &X_sync > SYNC 011111 -- ... --- .. ----- 1001010110 - @X_sync > EIEIO 011111 ----- ----- ----- 1101010110 - > +ISYNC 010011 ----- ----- ----- 0010010110 - > > # Condition Register Field Instruction > > diff --git a/target/ppc/translate.c b/target/ppc/translate.c > index 179cb69dc5..a31cda4490 100644 > --- a/target/ppc/translate.c > +++ b/target/ppc/translate.c > @@ -2727,20 +2727,6 @@ static inline void gen_check_tlb_flush(DisasContext > *ctx, bool global) > static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } > #endif > > -/* isync */ > -static void gen_isync(DisasContext *ctx) > -{ > - /* > - * We need to check for a pending TLB flush. This can only happen in > - * kernel mode however so check MSR_PR > - */ > - if (!ctx->pr) { > - gen_check_tlb_flush(ctx, false); > - } > - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); > - ctx->base.is_jmp = DISAS_EXIT_UPDATE; > -} > - > /* wait */ > static void gen_wait(DisasContext *ctx) > { > @@ -5377,7 +5363,6 @@ GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, > PPC_STRING), > GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), > GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), > GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), > -GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), > /* ISA v3.0 changed the extended opcode from 62 to 30 */ > GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT), > GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039CF801, PPC_NONE, PPC2_ISA300), > diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc > b/target/ppc/translate/storage-ctrl-impl.c.inc > index b8b4454663..943229c438 100644 > --- a/target/ppc/translate/storage-ctrl-impl.c.inc > +++ b/target/ppc/translate/storage-ctrl-impl.c.inc > @@ -155,6 +155,23 @@ static bool trans_SLBFEE(DisasContext *ctx, arg_SLBFEE > *a) > return true; > } > > +static bool trans_ISYNC(DisasContext *ctx, arg_ISYNC *a) > +{ > + REQUIRE_INSNS_FLAGS(ctx, MEM); > + > + /* > + * We need to check for a pending TLB flush. This can only happen in > + * kernel mode however so check MSR_PR > + */ > + if (!ctx->pr) { > + gen_check_tlb_flush(ctx, false); > + } > + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); > + ctx->base.is_jmp = DISAS_EXIT_UPDATE; > + > + return true; > +} > + > static bool trans_SLBSYNC(DisasContext *ctx, arg_SLBSYNC *a) > { > REQUIRE_64BIT(ctx); > -- > 2.55.0 >
