Hi Chen Pei, On Fri, 21 Aug 2026 16:19:50 +0800, Chen Pei wrote: > - hw/riscv/virt: The MMIO-window patch no longer touches the common > gpex code (Igor). The gpex_cfg.cxl_mmio32 field and the is_cxl > static _CRS branch are dropped; the ACPI0016 _CRS now comes from the > generic build_crs() path. Since EDK2 does not enumerate the pxb-cxl > expander bridge, riscv simulates the firmware PCI initialization > (reserved window + depth-first bridge bus numbers) and re-applies it > via a reset handler.
Ran this on master eea8fe61b8 (it still applies clean on bde2492aac). riscv64 bios-tables-test passes. In the generated DSDT the PC0C _CRS now comes out of build_crs() with the reserved window 0x70000000-0x7FFFFFFF and a bus range [0x0C,0x0D] taken from the real subordinate, PCI0 shrunk to 0x40000000-0x6FFFFFFF, and the CEDT CHBS and CFMWS matching the machine memmap. The machine-global window synthesis and the +15 bus range from v2 are gone. system_reset from the monitor leaves the root port with the same window and secondary/subordinate numbers, so the reset handler does what it says. One larger question on 3/4 about where that enumeration should come from, and a note on 4/4. Tested-by: Junjie Cao <[email protected]> Many thanks, Junjie
