The pcie FDT is quite tedious but can be parametrized into a helper. This is going to benefit only the 'virt' board for now but it will be used by the 'riscv-server-ref' board in the near future too.
Some other changes made: - FDT related macros are moved to fdt-common.h. Only a couple are being used by the helper ATM but more will be added in the next patches; - an RISCVAIAType enum is created. There are several FDTs that depends on the active AIA type being used, and we want a way to represent the different AIA modes that doesn't re-use the 'virt' specific VIRT_AIA_* macros. The enum vals are equivalent by design - we want "s->aia_type" to be used by 'virt' when calling the fdt helpers, and other boards will use "AIA_*" macros in their code. No FDT changes made. Signed-off-by: Daniel Henrique Barboza <[email protected]> Reviewed-by: Philippe Mathieu-Daudé <[email protected]> --- hw/riscv/fdt-common.c | 111 ++++++++++++++++++++++++++++++++++ hw/riscv/virt.c | 111 +++------------------------------- include/hw/riscv/fdt-common.h | 29 +++++++++ include/hw/riscv/virt.h | 15 ----- 4 files changed, 149 insertions(+), 117 deletions(-) diff --git a/hw/riscv/fdt-common.c b/hw/riscv/fdt-common.c index 0e3423acc8..54604d3158 100644 --- a/hw/riscv/fdt-common.c +++ b/hw/riscv/fdt-common.c @@ -15,6 +15,8 @@ #include "target/riscv/cpu_bits.h" #include "hw/riscv/riscv-iommu-bits.h" #include "hw/riscv/iommu.h" +#include "hw/pci/pci.h" +#include "hw/pci/pcie_host.h" void *riscv_create_board_device_tree(const char *model, const char *compatible, int *fdt_size) @@ -388,3 +390,112 @@ void riscv_create_fdt_riscv_iommu_sys(void *fdt, hwaddr addr, hwaddr size, *iommu_sys_phandle = iommu_phandle; } + +static void create_pcie_irq_map(void *fdt, char *nodename, + uint32_t irqchip_phandle, + RISCVAIAType aia_type, uint32_t pcie_irq) +{ + int pin, dev; + uint32_t irq_map_stride = 0; + uint32_t full_irq_map[PCI_NUM_PINS * PCI_NUM_PINS * + FDT_MAX_INT_MAP_WIDTH] = {}; + uint32_t *irq_map = full_irq_map; + + /* + * This code creates a standard swizzle of interrupts such that + * each device's first interrupt is based on it's PCI_SLOT number. + * (See pci_swizzle_map_irq_fn()) + * + * We only need one entry per interrupt in the table (not one per + * possible slot) seeing the interrupt-map-mask will allow the table + * to wrap to any number of devices. + */ + for (dev = 0; dev < PCI_NUM_PINS; dev++) { + int devfn = dev * 0x8; + + for (pin = 0; pin < PCI_NUM_PINS; pin++) { + int irq_nr = pcie_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); + int i = 0; + + /* Fill PCI address cells */ + irq_map[i] = cpu_to_be32(devfn << 8); + i += FDT_PCI_ADDR_CELLS; + + /* Fill PCI Interrupt cells */ + irq_map[i] = cpu_to_be32(pin + 1); + i += FDT_PCI_INT_CELLS; + + /* Fill interrupt controller phandle and cells */ + irq_map[i++] = cpu_to_be32(irqchip_phandle); + irq_map[i++] = cpu_to_be32(irq_nr); + + if (aia_type != AIA_TYPE_NONE) { + irq_map[i++] = cpu_to_be32(0x4); + } + + if (!irq_map_stride) { + irq_map_stride = i; + } + irq_map += irq_map_stride; + } + } + + qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map, + PCI_NUM_PINS * PCI_NUM_PINS * + irq_map_stride * sizeof(uint32_t)); + + qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", + 0x1800, 0, 0, 0x7); +} + +/* + * NOTE: this function uses a "/soc/pci@..." FDT subnode that + * should be created beforehand. + */ +void riscv_create_fdt_pcie(void *fdt, int aia_type, bool has_iommu_sys, + const MemMapEntry *pcie_ecam, + const MemMapEntry *pcie_pio, + const MemMapEntry *pcie_mmio, + const MemMapEntry *high_pcie, + uint32_t irq_pcie_phandle, + uint32_t msi_pcie_phandle, + uint32_t iommu_sys_phandle, uint32_t pcie_irq) +{ + g_autofree char *name = NULL; + + name = g_strdup_printf("/soc/pci@%"HWADDR_PRIx, pcie_ecam->base); + qemu_fdt_setprop_cell(fdt, name, "#address-cells", FDT_PCI_ADDR_CELLS); + qemu_fdt_setprop_cell(fdt, name, "#interrupt-cells", FDT_PCI_INT_CELLS); + qemu_fdt_setprop_cell(fdt, name, "#size-cells", 0x2); + qemu_fdt_setprop_string(fdt, name, "compatible", "pci-host-ecam-generic"); + qemu_fdt_setprop_string(fdt, name, "device_type", "pci"); + qemu_fdt_setprop_cell(fdt, name, "linux,pci-domain", 0); + + qemu_fdt_setprop_cells(fdt, name, "bus-range", 0, + pcie_ecam->size / PCIE_MMCFG_SIZE_MIN - 1); + qemu_fdt_setprop(fdt, name, "dma-coherent", NULL, 0); + + if (aia_type == AIA_TYPE_APLIC_IMSIC) { + qemu_fdt_setprop_cell(fdt, name, "msi-parent", msi_pcie_phandle); + } + + qemu_fdt_setprop_sized_cells(fdt, name, "reg", 2, + pcie_ecam->base, 2, pcie_ecam->size); + + qemu_fdt_setprop_sized_cells(fdt, name, "ranges", + 1, FDT_PCI_RANGE_IOPORT, 2, 0, + 2, pcie_pio->base, 2, pcie_pio->size, + 1, FDT_PCI_RANGE_MMIO, + 2, pcie_mmio->base, + 2, pcie_mmio->base, 2, pcie_mmio->size, + 1, FDT_PCI_RANGE_MMIO_64BIT, + 2, high_pcie->base, + 2, high_pcie->base, 2, high_pcie->size); + + if (has_iommu_sys) { + qemu_fdt_setprop_cells(fdt, name, "iommu-map", + 0, iommu_sys_phandle, 0, 0x10000); + } + + create_pcie_irq_map(fdt, name, irq_pcie_phandle, aia_type, pcie_irq); +} diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 211734c52b..32d66a278c 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -180,61 +180,6 @@ static void virt_flash_map(RISCVVirtState *s, sysmem); } -static void create_pcie_irq_map(RISCVVirtState *s, void *fdt, char *nodename, - uint32_t irqchip_phandle) -{ - int pin, dev; - uint32_t irq_map_stride = 0; - uint32_t full_irq_map[PCI_NUM_PINS * PCI_NUM_PINS * - FDT_MAX_INT_MAP_WIDTH] = {}; - uint32_t *irq_map = full_irq_map; - - /* - * This code creates a standard swizzle of interrupts such that - * each device's first interrupt is based on it's PCI_SLOT number. - * (See pci_swizzle_map_irq_fn()) - * - * We only need one entry per interrupt in the table (not one per - * possible slot) seeing the interrupt-map-mask will allow the table - * to wrap to any number of devices. - */ - for (dev = 0; dev < PCI_NUM_PINS; dev++) { - int devfn = dev * 0x8; - - for (pin = 0; pin < PCI_NUM_PINS; pin++) { - int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); - int i = 0; - - /* Fill PCI address cells */ - irq_map[i] = cpu_to_be32(devfn << 8); - i += FDT_PCI_ADDR_CELLS; - - /* Fill PCI Interrupt cells */ - irq_map[i] = cpu_to_be32(pin + 1); - i += FDT_PCI_INT_CELLS; - - /* Fill interrupt controller phandle and cells */ - irq_map[i++] = cpu_to_be32(irqchip_phandle); - irq_map[i++] = cpu_to_be32(irq_nr); - if (s->aia_type != VIRT_AIA_TYPE_NONE) { - irq_map[i++] = cpu_to_be32(0x4); - } - - if (!irq_map_stride) { - irq_map_stride = i; - } - irq_map += irq_map_stride; - } - } - - qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map, - PCI_NUM_PINS * PCI_NUM_PINS * - irq_map_stride * sizeof(uint32_t)); - - qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", - 0x1800, 0, 0, 0x7); -} - static void create_fdt_socket_aclint(RISCVVirtState *s, int socket, uint32_t *intc_phandles) @@ -722,51 +667,6 @@ static void create_fdt_virtio(RISCVVirtState *s, uint32_t irq_virtio_phandle) } } -static void create_fdt_pcie(RISCVVirtState *s, - uint32_t irq_pcie_phandle, - uint32_t msi_pcie_phandle, - uint32_t iommu_sys_phandle) -{ - g_autofree char *name = NULL; - MachineState *ms = MACHINE(s); - - name = g_strdup_printf("/soc/pci@%"HWADDR_PRIx, - s->memmap[VIRT_PCIE_ECAM].base); - qemu_fdt_setprop_cell(ms->fdt, name, "#address-cells", - FDT_PCI_ADDR_CELLS); - qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", - FDT_PCI_INT_CELLS); - qemu_fdt_setprop_cell(ms->fdt, name, "#size-cells", 0x2); - qemu_fdt_setprop_string(ms->fdt, name, "compatible", - "pci-host-ecam-generic"); - qemu_fdt_setprop_string(ms->fdt, name, "device_type", "pci"); - qemu_fdt_setprop_cell(ms->fdt, name, "linux,pci-domain", 0); - qemu_fdt_setprop_cells(ms->fdt, name, "bus-range", 0, - s->memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); - qemu_fdt_setprop(ms->fdt, name, "dma-coherent", NULL, 0); - if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { - qemu_fdt_setprop_cell(ms->fdt, name, "msi-parent", msi_pcie_phandle); - } - qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", 2, - s->memmap[VIRT_PCIE_ECAM].base, 2, s->memmap[VIRT_PCIE_ECAM].size); - qemu_fdt_setprop_sized_cells(ms->fdt, name, "ranges", - 1, FDT_PCI_RANGE_IOPORT, 2, 0, - 2, s->memmap[VIRT_PCIE_PIO].base, 2, s->memmap[VIRT_PCIE_PIO].size, - 1, FDT_PCI_RANGE_MMIO, - 2, s->memmap[VIRT_PCIE_MMIO].base, - 2, s->memmap[VIRT_PCIE_MMIO].base, 2, s->memmap[VIRT_PCIE_MMIO].size, - 1, FDT_PCI_RANGE_MMIO_64BIT, - 2, virt_high_pcie_memmap.base, - 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); - - if (virt_is_iommu_sys_enabled(s)) { - qemu_fdt_setprop_cells(ms->fdt, name, "iommu-map", - 0, iommu_sys_phandle, 0, 0x10000); - } - - create_pcie_irq_map(s, ms->fdt, name, irq_pcie_phandle); -} - static void create_fdt_uart(RISCVVirtState *s, uint32_t irq_mmio_phandle, int memId, int irqNo) { @@ -912,8 +812,15 @@ static void finalize_fdt(RISCVVirtState *s) irq_mmio_phandle, msi_pcie_phandle, &iommu_sys_phandle, IOMMU_SYS_IRQ); } - create_fdt_pcie(s, irq_pcie_phandle, msi_pcie_phandle, - iommu_sys_phandle); + + riscv_create_fdt_pcie(MACHINE(s)->fdt, s->aia_type, + virt_is_iommu_sys_enabled(s), + &s->memmap[VIRT_PCIE_ECAM], + &s->memmap[VIRT_PCIE_PIO], + &s->memmap[VIRT_PCIE_MMIO], + &virt_high_pcie_memmap, + irq_pcie_phandle, msi_pcie_phandle, + iommu_sys_phandle, PCIE_IRQ); riscv_create_fdt_syscon(MACHINE(s)->fdt, &phandle, s->memmap[VIRT_TEST].base, diff --git a/include/hw/riscv/fdt-common.h b/include/hw/riscv/fdt-common.h index 79463abfa5..7517316a56 100644 --- a/include/hw/riscv/fdt-common.h +++ b/include/hw/riscv/fdt-common.h @@ -11,6 +11,27 @@ #include "target/riscv/cpu.h" +#define FDT_PCI_ADDR_CELLS 3 +#define FDT_PCI_INT_CELLS 1 +#define FDT_PLIC_ADDR_CELLS 0 +#define FDT_PLIC_INT_CELLS 1 +#define FDT_APLIC_INT_CELLS 2 +#define FDT_APLIC_ADDR_CELLS 0 +#define FDT_IMSIC_INT_CELLS 0 +#define FDT_MAX_INT_CELLS 2 +#define FDT_MAX_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \ + 1 + FDT_MAX_INT_CELLS) +#define FDT_PLIC_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \ + 1 + FDT_PLIC_INT_CELLS) +#define FDT_APLIC_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \ + 1 + FDT_APLIC_INT_CELLS) + +typedef enum RISCVAIAType { + AIA_TYPE_NONE = 0, + AIA_TYPE_APLIC, + AIA_TYPE_APLIC_IMSIC, +} RISCVAIAType; + void *riscv_create_board_device_tree(const char *model, const char *compatible, int *fdt_size); void riscv_create_fdt_socket_memory(void *fdt, hwaddr addr, uint64_t size, @@ -48,4 +69,12 @@ void riscv_create_fdt_riscv_iommu_sys(void *fdt, hwaddr addr, hwaddr size, uint32_t msi_phandle, uint32_t *iommu_sys_phandle, uint32_t iommu_sys_irq); +void riscv_create_fdt_pcie(void *fdt, int aia_type, bool has_iommu_sys, + const MemMapEntry *pcie_ecam, + const MemMapEntry *pcie_pio, + const MemMapEntry *pcie_mmio, + const MemMapEntry *high_pcie, + uint32_t irq_pcie_phandle, + uint32_t msi_pcie_phandle, + uint32_t iommu_sys_phandle, uint32_t pcie_irq); #endif diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 7c862b0da2..e516898f9a 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -121,21 +121,6 @@ enum { #define VIRT_PLIC_SIZE(__num_context) \ (VIRT_PLIC_CONTEXT_BASE + (__num_context) * VIRT_PLIC_CONTEXT_STRIDE) -#define FDT_PCI_ADDR_CELLS 3 -#define FDT_PCI_INT_CELLS 1 -#define FDT_PLIC_ADDR_CELLS 0 -#define FDT_PLIC_INT_CELLS 1 -#define FDT_APLIC_INT_CELLS 2 -#define FDT_APLIC_ADDR_CELLS 0 -#define FDT_IMSIC_INT_CELLS 0 -#define FDT_MAX_INT_CELLS 2 -#define FDT_MAX_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \ - 1 + FDT_MAX_INT_CELLS) -#define FDT_PLIC_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \ - 1 + FDT_PLIC_INT_CELLS) -#define FDT_APLIC_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \ - 1 + FDT_APLIC_INT_CELLS) - bool virt_is_acpi_enabled(RISCVVirtState *s); bool virt_is_iommu_sys_enabled(RISCVVirtState *s); void virt_acpi_setup(RISCVVirtState *vms); -- 2.43.0
