include/hw/intc/riscv_aclint.h | 7 ++++---
hw/intc/riscv_aclint.c | 12 ++++++++----
hw/riscv/cps.c | 6 ++++--
hw/riscv/k230.c | 6 ++++--
hw/riscv/microchip_pfsoc.c | 5 +++--
hw/riscv/shakti_c.c | 7 ++++---
hw/riscv/sifive_e.c | 4 ++--
hw/riscv/sifive_u.c | 7 ++++---
hw/riscv/spike.c | 4 ++--
hw/riscv/tt_atlantis.c | 3 ++-
hw/riscv/virt.c | 17 +++++++++++------
hw/riscv/xiangshan_kmh.c | 6 ++++--
12 files changed, 52 insertions(+), 32 deletions(-)
diff --git a/include/hw/intc/riscv_aclint.h b/include/hw/intc/riscv_aclint.h
index 0e0b98acb08a..a8c5d4eb5895 100644
--- a/include/hw/intc/riscv_aclint.h
+++ b/include/hw/intc/riscv_aclint.h
@@ -46,7 +46,8 @@ typedef struct RISCVAclintMTimerState {
qemu_irq *timer_irqs;
} RISCVAclintMTimerState;
-DeviceState *riscv_aclint_mtimer_create(hwaddr addr, hwaddr size,
+DeviceState *riscv_aclint_mtimer_create(MemoryRegion *mr,
+ hwaddr addr, hwaddr size,
uint32_t hartid_base, uint32_t num_harts,
uint32_t timecmp_base, uint32_t time_base, uint32_t timebase_freq,
bool provide_rdtime);
@@ -68,8 +69,8 @@ typedef struct RISCVAclintSwiState {
qemu_irq *soft_irqs;
} RISCVAclintSwiState;
-DeviceState *riscv_aclint_swi_create(hwaddr addr, uint32_t hartid_base,
- uint32_t num_harts, bool sswi);
+DeviceState *riscv_aclint_swi_create(MemoryRegion *mr,
+ hwaddr addr, uint32_t hartid_base, uint32_t num_harts, bool sswi);
enum {
RISCV_ACLINT_DEFAULT_MTIMECMP = 0x0,
diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c
index 361a8d1bcb45..972c6c99b044 100644
--- a/hw/intc/riscv_aclint.c
+++ b/hw/intc/riscv_aclint.c
@@ -371,7 +371,8 @@ static const TypeInfo riscv_aclint_mtimer_info = {
/*
* Create ACLINT MTIMER device.
*/
-DeviceState *riscv_aclint_mtimer_create(hwaddr addr, hwaddr size,
+DeviceState *riscv_aclint_mtimer_create(MemoryRegion *mr,
+ hwaddr addr, hwaddr size,
uint32_t hartid_base, uint32_t num_harts,
uint32_t timecmp_base, uint32_t time_base, uint32_t timebase_freq,
bool provide_rdtime)
@@ -392,7 +393,8 @@ DeviceState *riscv_aclint_mtimer_create(hwaddr addr, hwaddr
size,
qdev_prop_set_uint32(dev, "aperture-size", size);
qdev_prop_set_uint32(dev, "timebase-freq", timebase_freq);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
- sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
+ memory_region_add_subregion(mr, addr,
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0));
for (i = 0; i < num_harts; i++) {
CPUState *cpu = cpu_by_arch_id(hartid_base + i);
@@ -556,7 +558,8 @@ static const TypeInfo riscv_aclint_swi_info = {
/*
* Create ACLINT [M|S]SWI device.
*/
-DeviceState *riscv_aclint_swi_create(hwaddr addr, uint32_t hartid_base,
+DeviceState *riscv_aclint_swi_create(MemoryRegion *mr,
+ hwaddr addr, uint32_t hartid_base,
uint32_t num_harts, bool sswi)
{
int i;
@@ -569,7 +572,8 @@ DeviceState *riscv_aclint_swi_create(hwaddr addr, uint32_t
hartid_base,
qdev_prop_set_uint32(dev, "num-harts", num_harts);
qdev_prop_set_uint32(dev, "sswi", sswi ? true : false);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
- sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
+ memory_region_add_subregion(mr, addr,
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0));
for (i = 0; i < num_harts; i++) {
CPUState *cpu = cpu_by_arch_id(hartid_base + i);
diff --git a/hw/riscv/cps.c b/hw/riscv/cps.c
index 86172be5b3ca..5cfb54aa27d2 100644
--- a/hw/riscv/cps.c
+++ b/hw/riscv/cps.c
@@ -151,9 +151,11 @@ static void riscv_cps_realize(DeviceState *dev, Error
**errp)
false, false, s->aplic);
/* PLIC changes msi_nonbroken to ture. We revert the change. */
msi_nonbroken = false;
- riscv_aclint_swi_create(cm_base + AIA_CLINT_OFFSET,
+ riscv_aclint_swi_create(get_system_memory(),
+ cm_base + AIA_CLINT_OFFSET,
hartid_base, MAX_HARTS, false);
- riscv_aclint_mtimer_create(cm_base + AIA_CLINT_OFFSET +
+ riscv_aclint_mtimer_create(get_system_memory(),
+ cm_base + AIA_CLINT_OFFSET +
RISCV_ACLINT_SWI_SIZE,
RISCV_ACLINT_DEFAULT_MTIMER_SIZE,
hartid_base,
diff --git a/hw/riscv/k230.c b/hw/riscv/k230.c
index 558f30b97e9d..1ef4260c5391 100644
--- a/hw/riscv/k230.c
+++ b/hw/riscv/k230.c
@@ -196,9 +196,11 @@ static void k230_soc_realize(DeviceState *dev, Error
**errp)
s->c908_plic = k230_create_plic(C908_CPU_HARTID, c908_cpus);
/* CLINT */
- riscv_aclint_swi_create(memmap[K230_DEV_CLINT].base,
+ riscv_aclint_swi_create(sys_mem,
+ memmap[K230_DEV_CLINT].base,
C908_CPU_HARTID, c908_cpus, false);
- riscv_aclint_mtimer_create(memmap[K230_DEV_CLINT].base + 0x4000,
+ riscv_aclint_mtimer_create(sys_mem,
+ memmap[K230_DEV_CLINT].base + 0x4000,
RISCV_ACLINT_DEFAULT_MTIMER_SIZE,
C908_CPU_HARTID, c908_cpus,
RISCV_ACLINT_DEFAULT_MTIMECMP,
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 4017129c8304..a6026776d4de 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -250,9 +250,10 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev,
Error **errp)
memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].size);
/* CLINT */
- riscv_aclint_swi_create(memmap[MICROCHIP_PFSOC_CLINT].base,
+ riscv_aclint_swi_create(system_memory,
+ memmap[MICROCHIP_PFSOC_CLINT].base,
0, ms->smp.cpus, false);
- riscv_aclint_mtimer_create(
+ riscv_aclint_mtimer_create(system_memory,
memmap[MICROCHIP_PFSOC_CLINT].base + RISCV_ACLINT_SWI_SIZE,
RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus,
RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
index 835b1f879b7f..86ff8f8fcaab 100644
--- a/hw/riscv/shakti_c.c
+++ b/hw/riscv/shakti_c.c
@@ -127,10 +127,11 @@ static void shakti_c_soc_state_realize(DeviceState *dev,
Error **errp)
SHAKTI_C_PLIC_CONTEXT_STRIDE,
shakti_c_memmap[SHAKTI_C_PLIC].size);
- riscv_aclint_swi_create(shakti_c_memmap[SHAKTI_C_CLINT].base,
+ riscv_aclint_swi_create(system_memory,
+ shakti_c_memmap[SHAKTI_C_CLINT].base,
0, 1, false);
- riscv_aclint_mtimer_create(shakti_c_memmap[SHAKTI_C_CLINT].base +
- RISCV_ACLINT_SWI_SIZE,
+ riscv_aclint_mtimer_create(system_memory,
+ shakti_c_memmap[SHAKTI_C_CLINT].base + RISCV_ACLINT_SWI_SIZE,
RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, 1,
RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, false);
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 71925583bd97..0ea444f43bc5 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -225,9 +225,9 @@ static void sifive_e_soc_realize(DeviceState *dev, Error
**errp)
SIFIVE_E_PLIC_CONTEXT_BASE,
SIFIVE_E_PLIC_CONTEXT_STRIDE,
memmap[SIFIVE_E_DEV_PLIC].size);
- riscv_aclint_swi_create(memmap[SIFIVE_E_DEV_CLINT].base,
+ riscv_aclint_swi_create(sys_mem, memmap[SIFIVE_E_DEV_CLINT].base,
0, ms->smp.cpus, false);
- riscv_aclint_mtimer_create(memmap[SIFIVE_E_DEV_CLINT].base +
+ riscv_aclint_mtimer_create(sys_mem, memmap[SIFIVE_E_DEV_CLINT].base +
RISCV_ACLINT_SWI_SIZE,
RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus,
RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 57a57c96e16b..58b4744318f8 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -788,10 +788,11 @@ static void sifive_u_soc_realize(DeviceState *dev, Error
**errp)
serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART1].base,
serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ));
- riscv_aclint_swi_create(memmap[SIFIVE_U_DEV_CLINT].base, 0,
+ riscv_aclint_swi_create(system_memory,
+ memmap[SIFIVE_U_DEV_CLINT].base, 0,
ms->smp.cpus, false);
- riscv_aclint_mtimer_create(memmap[SIFIVE_U_DEV_CLINT].base +
- RISCV_ACLINT_SWI_SIZE,
+ riscv_aclint_mtimer_create(system_memory,
+ memmap[SIFIVE_U_DEV_CLINT].base + RISCV_ACLINT_SWI_SIZE,
RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus,
RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
CLINT_TIMEBASE_FREQ, false);
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 630b65f56977..a227e0eca147 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -163,10 +163,10 @@ static void spike_board_init(MachineState *machine)
sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal);
/* Core Local Interruptor (timer and IPI) for each socket */
- riscv_aclint_swi_create(
+ riscv_aclint_swi_create(system_memory,
memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size,
base_hartid, hart_count, false);
- riscv_aclint_mtimer_create(
+ riscv_aclint_mtimer_create(system_memory,
memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size +
RISCV_ACLINT_SWI_SIZE,
RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count,
diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c
index d69851df0a01..3f183db5c302 100644
--- a/hw/riscv/tt_atlantis.c
+++ b/hw/riscv/tt_atlantis.c
@@ -509,7 +509,8 @@ static void tt_atlantis_machine_init(MachineState *machine)
TT_IRQCHIP_NUM_MSIS,
TT_IRQCHIP_NUM_PRIO_BITS);
- riscv_aclint_mtimer_create(s->memmap[TT_ATL_ACLINT].base,
+ riscv_aclint_mtimer_create(system_memory,
+ s->memmap[TT_ATL_ACLINT].base,
TT_ACLINT_MTIME_SIZE,
0, hart_count,
TT_ACLINT_MTIMECMP,
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 22a607ed10bf..6e4b39315aaa 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -1370,7 +1370,8 @@ static void virt_machine_init(MachineState *machine)
if (virt_aclint_allowed() && s->have_aclint) {
if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
/* Per-socket ACLINT MTIMER */
- riscv_aclint_mtimer_create(s->memmap[VIRT_CLINT].base +
+ riscv_aclint_mtimer_create(system_memory,
+ s->memmap[VIRT_CLINT].base +
i * RISCV_ACLINT_DEFAULT_MTIMER_SIZE,
RISCV_ACLINT_DEFAULT_MTIMER_SIZE,
base_hartid, hart_count,
@@ -1379,10 +1380,12 @@ static void virt_machine_init(MachineState *machine)
RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
} else {
/* Per-socket ACLINT MSWI, MTIMER, and SSWI */
- riscv_aclint_swi_create(s->memmap[VIRT_CLINT].base +
+ riscv_aclint_swi_create(system_memory,
+ s->memmap[VIRT_CLINT].base +
i * s->memmap[VIRT_CLINT].size,
base_hartid, hart_count, false);
- riscv_aclint_mtimer_create(s->memmap[VIRT_CLINT].base +
+ riscv_aclint_mtimer_create(system_memory,
+ s->memmap[VIRT_CLINT].base +
i * s->memmap[VIRT_CLINT].size +
RISCV_ACLINT_SWI_SIZE,
RISCV_ACLINT_DEFAULT_MTIMER_SIZE,
@@ -1390,16 +1393,18 @@ static void virt_machine_init(MachineState *machine)
RISCV_ACLINT_DEFAULT_MTIMECMP,
RISCV_ACLINT_DEFAULT_MTIME,
RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
- riscv_aclint_swi_create(s->memmap[VIRT_ACLINT_SSWI].base +
+ riscv_aclint_swi_create(system_memory,
+ s->memmap[VIRT_ACLINT_SSWI].base +
i * s->memmap[VIRT_ACLINT_SSWI].size,
base_hartid, hart_count, true);
}
} else if (tcg_enabled()) {
/* Per-socket SiFive CLINT */
- riscv_aclint_swi_create(
+ riscv_aclint_swi_create(system_memory,
s->memmap[VIRT_CLINT].base + i *
s->memmap[VIRT_CLINT].size,
base_hartid, hart_count, false);
- riscv_aclint_mtimer_create(s->memmap[VIRT_CLINT].base +
+ riscv_aclint_mtimer_create(system_memory,
+ s->memmap[VIRT_CLINT].base +
i * s->memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZE,
RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count,
RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
diff --git a/hw/riscv/xiangshan_kmh.c b/hw/riscv/xiangshan_kmh.c
index 384624d69ad5..94f9d02a00b9 100644
--- a/hw/riscv/xiangshan_kmh.c
+++ b/hw/riscv/xiangshan_kmh.c
@@ -116,9 +116,11 @@ static void xiangshan_kmh_soc_realize(DeviceState *dev,
Error **errp)
115200, serial_hd(0), DEVICE_LITTLE_ENDIAN);
/* CLINT */
- riscv_aclint_swi_create(memmap[XIANGSHAN_KMH_CLINT].base,
+ riscv_aclint_swi_create(system_memory,
+ memmap[XIANGSHAN_KMH_CLINT].base,
0, num_harts, false);
- riscv_aclint_mtimer_create(memmap[XIANGSHAN_KMH_CLINT].base +
+ riscv_aclint_mtimer_create(system_memory,
+ memmap[XIANGSHAN_KMH_CLINT].base +
RISCV_ACLINT_SWI_SIZE,
RISCV_ACLINT_DEFAULT_MTIMER_SIZE,
0, num_harts, RISCV_ACLINT_DEFAULT_MTIMECMP,
