On 8/26/2026 9:33 AM, Zongmin Zhou wrote:
From: Zongmin Zhou <[email protected]> The RISC-V ISA manual used to (incorrectly) state that the JVT CSR and the cm.jalt/cm.jt instructions are controlled by mstateen0/hstateen0 bit 2. That text was spurious and has been removed from the spec by riscv/riscv-isa-manual PR #2637 (merged 2026-02-05, closing issue #2620). Drop the corresponding smstateen_acc_ok() checks from the Zcmt CSR predicate and the cm_jalt() helper, along with the now unused SMSTATEEN0_JVT definition, so that JVT accesses are no longer incorrectly trapped when stateen0 bit 2 is clear. Reference: https://github.com/riscv/riscv-isa-manual/pull/2637 Signed-off-by: Zongmin Zhou <[email protected]> ---
Reviewed-by: Daniel Henrique Barboza <[email protected]>
target/riscv/cpu_bits.h | 1 - target/riscv/tcg/csr.c | 7 ------- target/riscv/tcg/zce_helper.c | 7 ------- 3 files changed, 15 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index c01050ce2b..11648abecf 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -354,7 +354,6 @@ #define SMSTATEEN_MAX_COUNT 4 #define SMSTATEEN0_CS (1ULL << 0) #define SMSTATEEN0_FCSR (1ULL << 1) -#define SMSTATEEN0_JVT (1ULL << 2) #define SMSTATEEN0_CTR (1ULL << 54) #define SMSTATEEN0_P1P13 (1ULL << 56) #define SMSTATEEN0_HSCONTXT (1ULL << 57) diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c index 78fdd14a08..967626be75 100644 --- a/target/riscv/tcg/csr.c +++ b/target/riscv/tcg/csr.c @@ -180,13 +180,6 @@ static RISCVException zcmt(CPURISCVState *env, int csrno) return RISCV_EXCP_ILLEGAL_INST; }-#if !defined(CONFIG_USER_ONLY)- RISCVException ret = smstateen_acc_ok(env, 0, SMSTATEEN0_JVT); - if (ret != RISCV_EXCP_NONE) { - return ret; - } -#endif - return RISCV_EXCP_NONE; }diff --git a/target/riscv/tcg/zce_helper.c b/target/riscv/tcg/zce_helper.cindex c6ba4c1a47..2fa8945b2d 100644 --- a/target/riscv/tcg/zce_helper.c +++ b/target/riscv/tcg/zce_helper.c @@ -28,13 +28,6 @@ target_ulong HELPER(cm_jalt)(CPURISCVState *env, uint32_t index) MemOp endian = mo_endian_env(env); MemOpIdx oi;-#if !defined(CONFIG_USER_ONLY)- RISCVException ret = smstateen_acc_ok(env, 0, SMSTATEEN0_JVT); - if (ret != RISCV_EXCP_NONE) { - riscv_raise_exception(env, ret, 0); - } -#endif - target_ulong target; target_ulong val = env->jvt; int xlen = riscv_cpu_xlen(env);
