From: Jason Chien <[email protected]> Add disassembler support for all SiFive custom int8 matrix-multiply instructions: sf.vqmacc{u,,us,su}.4x8x4 and sf.vqmacc{u,,us,su}.2x8x2.
These instructions share opcode 0b1011011 and funct3 0b010, and are distinguished by funct6: 60-63 for the 4x8x4 (Xsfvqmaccqoq) tile and 44-47 for the 2x8x2 (Xsfvqmaccdod) tile. Signed-off-by: Jason Chien <[email protected]> Reviewed-by: Daniel Henrique Barboza <[email protected]> Signed-off-by: Max Chou <[email protected]> --- MAINTAINERS | 1 + disas/meson.build | 3 ++- disas/riscv-xsf-op.c.inc | 11 +++++++++ disas/riscv-xsf.c | 49 ++++++++++++++++++++++++++++++++++++++++ disas/riscv-xsf.h | 16 +++++++++++++ disas/riscv.c | 2 ++ disas/riscv.h | 1 + 7 files changed, 82 insertions(+), 1 deletion(-) create mode 100644 disas/riscv-xsf-op.c.inc create mode 100644 disas/riscv-xsf.c create mode 100644 disas/riscv-xsf.h diff --git a/MAINTAINERS b/MAINTAINERS index 2e8dace19ff..629a238c925 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -405,6 +405,7 @@ S: Supported F: target/riscv/xsf.decode F: target/riscv/tcg/insn_trans/trans_xsf.c.inc F: target/riscv/tcg/xsf_helper.c +F: disas/riscv-xsf* RENESAS RX CPUs R: Yoshinori Sato <[email protected]> diff --git a/disas/meson.build b/disas/meson.build index 42977a1f74d..91357162682 100644 --- a/disas/meson.build +++ b/disas/meson.build @@ -8,7 +8,8 @@ common_ss.add(when: 'CONFIG_RISCV_DIS', if_true: files( 'riscv.c', 'riscv-xthead.c', 'riscv-xventana.c', - 'riscv-xlrbr.c' + 'riscv-xlrbr.c', + 'riscv-xsf.c' )) common_ss.add(when: 'CONFIG_SH4_DIS', if_true: files('sh4.c')) common_ss.add(when: 'CONFIG_SPARC_DIS', if_true: files('sparc.c')) diff --git a/disas/riscv-xsf-op.c.inc b/disas/riscv-xsf-op.c.inc new file mode 100644 index 00000000000..c8daa7ebef8 --- /dev/null +++ b/disas/riscv-xsf-op.c.inc @@ -0,0 +1,11 @@ +/* Xsfvqmaccqoq */ +OP(sf_vqmaccu_4x8x4, "sf.vqmaccu.4x8x4", rv_codec_v_r, rv_fmt_vd_vs1_vs2) +OP(sf_vqmacc_4x8x4, "sf.vqmacc.4x8x4", rv_codec_v_r, rv_fmt_vd_vs1_vs2) +OP(sf_vqmaccus_4x8x4, "sf.vqmaccus.4x8x4", rv_codec_v_r, rv_fmt_vd_vs1_vs2) +OP(sf_vqmaccsu_4x8x4, "sf.vqmaccsu.4x8x4", rv_codec_v_r, rv_fmt_vd_vs1_vs2) + +/* Xsfvqmaccdod */ +OP(sf_vqmaccu_2x8x2, "sf.vqmaccu.2x8x2", rv_codec_v_r, rv_fmt_vd_vs1_vs2) +OP(sf_vqmacc_2x8x2, "sf.vqmacc.2x8x2", rv_codec_v_r, rv_fmt_vd_vs1_vs2) +OP(sf_vqmaccus_2x8x2, "sf.vqmaccus.2x8x2", rv_codec_v_r, rv_fmt_vd_vs1_vs2) +OP(sf_vqmaccsu_2x8x2, "sf.vqmaccsu.2x8x2", rv_codec_v_r, rv_fmt_vd_vs1_vs2) diff --git a/disas/riscv-xsf.c b/disas/riscv-xsf.c new file mode 100644 index 00000000000..745fcc8efda --- /dev/null +++ b/disas/riscv-xsf.c @@ -0,0 +1,49 @@ +/* + * QEMU RISC-V Disassembler for xsf (SiFive vendor extensions). + * + * Copyright (c) 2023 SiFive, Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "disas/riscv.h" +#include "disas/riscv-xsf.h" + +#define OP(N, ...) static const rv_opcode_data op_##N = { __VA_ARGS__ }; +#include "riscv-xsf-op.c.inc" +#undef OP + +const rv_opcode_data *decode_xsf(rv_decode *dec, rv_isa isa) +{ + rv_inst inst = dec->inst; + + switch ((inst >> 0) & 0b1111111) { + case 0b1011011: + switch ((inst >> 12) & 0b111) { + case 0b010: + switch ((inst >> 26) & 0b111111) { + case 0b101100: + return &op_sf_vqmaccu_2x8x2; + case 0b101101: + return &op_sf_vqmacc_2x8x2; + case 0b101110: + return &op_sf_vqmaccus_2x8x2; + case 0b101111: + return &op_sf_vqmaccsu_2x8x2; + case 0b111100: + return &op_sf_vqmaccu_4x8x4; + case 0b111101: + return &op_sf_vqmacc_4x8x4; + case 0b111110: + return &op_sf_vqmaccus_4x8x4; + case 0b111111: + return &op_sf_vqmaccsu_4x8x4; + } + break; + } + break; + } + + return NULL; +} diff --git a/disas/riscv-xsf.h b/disas/riscv-xsf.h new file mode 100644 index 00000000000..b15b7aa97c8 --- /dev/null +++ b/disas/riscv-xsf.h @@ -0,0 +1,16 @@ +/* + * QEMU disassembler -- RISC-V specific header (xsf*). + * + * Copyright (c) 2023 SiFive, Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef DISAS_RISCV_XSF_H +#define DISAS_RISCV_XSF_H + +#include "disas/riscv.h" + +const rv_opcode_data *decode_xsf(rv_decode *, rv_isa); + +#endif /* DISAS_RISCV_XSF_H */ diff --git a/disas/riscv.c b/disas/riscv.c index e85dbac0351..60d934744de 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -27,6 +27,7 @@ #include "disas/riscv-xthead.h" #include "disas/riscv-xventana.h" #include "disas/riscv-xlrbr.h" +#include "disas/riscv-xsf.h" /* register names */ @@ -3457,6 +3458,7 @@ static GString *disasm_inst(rv_isa isa, uint64_t pc, rv_inst inst, { has_xtheadsync_p, decode_xtheadsync }, { has_XVentanaCondOps_p, decode_xventanacondops }, { has_xlrbr_p, decode_xlrbr }, + { has_xsf_p, decode_xsf }, }; for (size_t i = 0; i < ARRAY_SIZE(decoders); i++) { diff --git a/disas/riscv.h b/disas/riscv.h index b0269bb709f..4f1ffc4ae02 100644 --- a/disas/riscv.h +++ b/disas/riscv.h @@ -262,6 +262,7 @@ typedef struct { #define rv_fmt_vd_vs2_imm_vm "O\tD,F,im" #define rv_fmt_vd_vs2_uimm "O\tD,F,u" #define rv_fmt_vd_vs2_uimm_vm "O\tD,F,um" +#define rv_fmt_vd_vs1_vs2 "O\tD,E,F" #define rv_fmt_vd_vs1_vs2_vm "O\tD,E,Fm" #define rv_fmt_vd_rs1_vs2_vm "O\tD,1,Fm" #define rv_fmt_vd_fs1_vs2_vm "O\tD,4,Fm" -- 2.43.0
