On Tue, 18 Aug 2026 at 00:13, Anirudh Srinivasan
<[email protected]> wrote:
>
> Atlantis has 4 PRCMs that are visible from S mode by the Ascalon Core
> (RCPU, HSIO, PCIe and MM). This commit adds these 4 PRCM blocks to the
> tt-atlantis model, along with necessary device tree nodes for them.
>
> Reviewed-by: Chao Liu <[email protected]>
> Signed-off-by: Anirudh Srinivasan <[email protected]>
> ---
> docs/system/riscv/tt_atlantis.rst | 1 +
> hw/riscv/tt_atlantis.c | 94
> +++++++++++++++++++++++++++++++++++++++
> include/hw/riscv/tt_atlantis.h | 19 ++++++++
> 3 files changed, 114 insertions(+)
>
> diff --git a/docs/system/riscv/tt_atlantis.rst
> b/docs/system/riscv/tt_atlantis.rst
> index 1f2880d617..539c22354f 100644
> --- a/docs/system/riscv/tt_atlantis.rst
> +++ b/docs/system/riscv/tt_atlantis.rst
> @@ -14,6 +14,7 @@ tt-atlantis QEMU model features
> * 8-core Ascalon-X CPU Cluster
> * RISC-V compliant Advanced Interrupt Architecture
> * 16550A compatible UART
> +* 4 PRCMs (Clock and Reset Controllers)
>
> Known limitations
> -----------------
> diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c
> index d808bcc11c..9ebba07703 100644
> --- a/hw/riscv/tt_atlantis.c
> +++ b/hw/riscv/tt_atlantis.c
> @@ -26,6 +26,7 @@
> #include "hw/char/serial-mm.h"
> #include "hw/intc/riscv_aclint.h"
> #include "hw/misc/unimp.h"
> +#include "hw/misc/tt_atlantis_prcm.h"
>
> #include "system/system.h"
> #include "system/device_tree.h"
> @@ -59,6 +60,10 @@ static const MemMapEntry tt_atlantis_memmap[] = {
> [TT_ATL_I2C3] = { 0xd4070000, 0x10000 },
> [TT_ATL_I2C4] = { 0xd4080000, 0x10000 },
> [TT_ATL_UART1] = { 0xd4110000, 0x10000 },
> + [TT_ATL_PRCM_RCPU] = { 0xd0000000, 0x10000 },
> + [TT_ATL_PRCM_PCIE] = { 0xd8000000, 0x100 },
> + [TT_ATL_PRCM_MM] = { 0xdc000000, 0x1000 },
> + [TT_ATL_PRCM_HSIO] = { 0xe00c0000, 0x510 },
> [TT_ATL_SAPLIC] = { 0xe8000000, 0x4000000 },
> [TT_ATL_DDR_HI] = { 0x100000000, 0x1000000000 },
> };
> @@ -328,11 +333,35 @@ static void create_fdt_i2c_device(TTAtlantisState *s,
> int bus,
> qemu_fdt_setprop_cell(fdt, name, "reg", addr);
> }
>
> +static char *create_fdt_prcm(void *fdt, const MemMapEntry *mem,
> + const char *prcm_name)
> +{
> + hwaddr base = mem->base;
> + hwaddr size = mem->size;
> + char *name = g_strdup_printf("/soc/prcm_%s@%" PRIx64,
> + prcm_name, mem->base);
Use the locals, or drop them and use mem->base both times.
> + g_autofree char *compatible =
> + g_strdup_printf("tenstorrent,atlantis-prcm-%s", prcm_name);
> +
> + qemu_fdt_add_subnode(fdt, name);
> + qemu_fdt_setprop_string(fdt, name, "compatible", compatible);
> + qemu_fdt_setprop_sized_cells(fdt, name, "reg", 2, base, 2, size);
> + qemu_fdt_setprop_cell(fdt, name, "#address-cells", 1);
> + qemu_fdt_setprop_cell(fdt, name, "#size-cells", 0);
> + qemu_fdt_setprop_cell(fdt, name, "#clock-cells", 1);
> + qemu_fdt_setprop_cell(fdt, name, "#reset-cells", 1);
> + qemu_fdt_setprop_cell(fdt, name, "phandle", next_phandle());
If a phandle falls in the woods and nobody...
If you're not saving this value anywhere, is there any need to set one?
> +
> + return name;
> +}
> +
> static void finalize_fdt(TTAtlantisState *s)
> {
> uint32_t aplic_s_phandle = next_phandle();
> uint32_t imsic_s_phandle = next_phandle();
> uint32_t periph_clk_phandle = next_phandle();
> + uint32_t osc_24m_phandle = next_phandle();
> + uint32_t prcm_rcpu_phandle;
> void *fdt = MACHINE(s)->fdt;
>
> create_fdt_cpu(s, s->memmap, aplic_s_phandle, imsic_s_phandle);
> @@ -348,6 +377,34 @@ static void finalize_fdt(TTAtlantisState *s)
> aplic_s_phandle);
>
> create_fdt_clk(fdt, "periph-clk", 100000000, periph_clk_phandle);
> + create_fdt_clk(fdt, "osc_24m", 24000000, osc_24m_phandle);
With the PRCM enabled the UART and I2C can get a real clock? So we can
drop the periph-clk node and modify create_fdt_i2c as well as
create_fdt_uart to use the real PRCM phandles. This will shake out any
issues with how you're wiring up the device tree too.
> +
> + g_autofree char *rcpu_name = create_fdt_prcm(fdt,
> + &s->memmap[TT_ATL_PRCM_RCPU], "rcpu");
> + prcm_rcpu_phandle = qemu_fdt_get_phandle(fdt, rcpu_name);
This is a great function that I didn't know of when I wrote
next_phandle(). I'm all for using it, but lets swap the entire file
over at once.
> + qemu_fdt_setprop_cells(fdt, rcpu_name, "clocks", osc_24m_phandle);
> + qemu_fdt_setprop_cells(fdt, rcpu_name, "assigned-clocks",
> + prcm_rcpu_phandle, TT_ATL_CLK_RCPU_ROOT,
> + prcm_rcpu_phandle, TT_ATL_CLK_NOCC_CLK);
> + qemu_fdt_setprop_cells(fdt, rcpu_name, "assigned-clock-parents",
> + prcm_rcpu_phandle, TT_ATL_CLK_RCPU_PLL,
> + prcm_rcpu_phandle, TT_ATL_CLK_NOC_PLL);
> @@ -545,6 +602,43 @@ static void tt_atlantis_machine_init(MachineState
> *machine)
> serial_mm_init(system_memory, s->memmap[TT_ATL_UART1].base, 2,
> qdev_get_gpio_in(s->irqchip, TT_ATL_UART1_IRQ),
> 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN);
> +
> + /* Add rcpu prcm block */
> + object_initialize_child(OBJECT(s), "prcm-rcpu", &s->prcm[0],
> + TYPE_TT_ATLANTIS_PRCM_RCPU);
> + sysbus_realize(SYS_BUS_DEVICE(&s->prcm[0]), &error_fatal);
> + memory_region_add_subregion(system_memory,
Since you're already sending a v3, can you rebase it on this series please:
https://lore.kernel.org/qemu-riscv/[email protected]/
Aside from code shuffling, you will pass s->memory to
memory_region_add_subregion, the _realize calls go in
tt_atlantis_soc_realize, and the initalise calls go in
tt_atlantis_soc_init.
> + s->memmap[TT_ATL_PRCM_RCPU].base,
> + sysbus_mmio_get_region(
> + SYS_BUS_DEVICE(&s->prcm[0]), 0));
> +
> diff --git a/include/hw/riscv/tt_atlantis.h b/include/hw/riscv/tt_atlantis.h
> index 7f7d4a5a59..20bcdfeb52 100644
> --- a/include/hw/riscv/tt_atlantis.h
> +++ b/include/hw/riscv/tt_atlantis.h
> @@ -59,6 +62,22 @@ enum {
> TT_ATL_SAPLIC,
> TT_ATL_SIMSIC,
> TT_ATL_UART1,
> + TT_ATL_PRCM_RCPU,
> + TT_ATL_PRCM_HSIO,
> + TT_ATL_PRCM_PCIE,
> + TT_ATL_PRCM_MM,
> +};
> +
> +/* RCPU PRCM Clock IDs */
Do these come from
include/dt-bindings/clock/tenstorrent,atlantis-prcm-rcpu.h in linux?
Add a comment.
> +enum {
> + TT_ATL_CLK_RCPU_PLL = 0,
> + TT_ATL_CLK_RCPU_ROOT = 1,
> + TT_ATL_CLK_NOC_PLL = 25,
> + TT_ATL_CLK_NOCC_CLK = 26,
> + TT_ATL_CLK_HSIO_PLL = 54,
> + TT_ATL_CLK_PCIE_PLL = 55,
> + TT_ATL_CLK_MM_PLL0 = 56,
> + TT_ATL_CLK_MM_PLL1 = 57,
> };
>
> #endif
>
> --
> 2.43.0
>
