On Fri, Jul 24, 2026 at 8:11 AM Pierrick Bouvier <
[email protected]> wrote:
>
> Signed-off-by: Pierrick Bouvier <[email protected]>
> ---
> include/qemu/target-info.h | 16 +++++++++++++++-
> target-info.c | 16 ++++++++++++++++
> 2 files changed, 31 insertions(+), 1 deletion(-)
>
> diff --git a/include/qemu/target-info.h b/include/qemu/target-info.h
> index 6c5b714288e..88ccef2a988 100644
> --- a/include/qemu/target-info.h
> +++ b/include/qemu/target-info.h
> @@ -99,10 +99,24 @@ bool target_ppc64(void);
> */
> bool target_s390x(void);
>
> +/**
> + * target_base_riscv:
> + *
> + * Returns whether the target architecture is RISC-V 32-bit or 64-bit.
> + */
> +bool target_base_riscv(void);
> +
> +/**
> + * target_riscv32:
> + *
> + * Returns whether the target architecture is RISC-V 32-bit.
> + */
> +bool target_riscv32(void);
> +
> /**
> * target_riscv64:
> *
> - * Returns whether the target architecture is riscv64
> + * Returns whether the target architecture is RISC-V 64-bit.
> */
> bool target_riscv64(void);
>
> diff --git a/target-info.c b/target-info.c
> index 04c69c41f8a..7ac2260b182 100644
> --- a/target-info.c
> +++ b/target-info.c
> @@ -94,6 +94,22 @@ bool target_s390x(void)
> return target_arch() == SYS_EMU_TARGET_S390X;
> }
>
> +bool target_base_riscv(void)
> +{
> + switch (target_arch()) {
> + case SYS_EMU_TARGET_RISCV32:
> + case SYS_EMU_TARGET_RISCV64:
> + return true;
> + default:
> + return false;
> + }
This can be improved by using (TARGET_ARCH_BITMASK(target_arch()) &
QEMU_ARCH_RISCV
TARGET_ARCH_BITMASK should be a new macro in base-arch-defs.h
#define TARGET_ARCH_BITMASK(sys_emu) 1UL << (sys_emu)
And the enum in base-arch-defs.h can be update with this emu, so once the
sys_emu maximal >32 still works in future.
> +}
> +
> +bool target_riscv32(void)
> +{
> + return target_arch() == SYS_EMU_TARGET_RISCV32;
> +}
> +
> bool target_riscv64(void)
> {
> return target_arch() == SYS_EMU_TARGET_RISCV64;
> --
> 2.43.0
>
>
--
此致
礼
罗勇刚
Yours
sincerely,
Yonggang Luo
