On 9/1/2026 1:05 AM, Peter Xu wrote: > On Mon, Aug 31, 2026 at 05:46:12PM +0200, Philippe Mathieu-Daudé wrote: >> On 31/8/26 13:49, BillXiang wrote: >> >>> How about discussing the patch[1]: >>> "virtio: Add aligned ld/st accessors for vring". >>> >>> As pointed out in the patch, this has been a long-standing issue. It is >>> now necessary to introduce atomic accessors for fields that require >>> atomicity, such as the avail_idx field in virtio. This support is >>> especially crucial for architectures like RISC-V, which do not natively >>> support misaligned memory accesses. >>> >>> I'm particularly eager to receive more suggestions for it. > > I saw the last email was from me.. > > https://lore.kernel.org/qemu-devel/[email protected]/ > > I believe that was what PeterM suggested. I think Richard also at least > partly agrees. so I thought we had at least partial consensus on the rough > idea, if not exactly how. > > I confess I haven't fully got the latter part of Richard's comment, > regarding the possibility to reuse accel/tcg/ldst_atomicity.c.inc: that > path seems to invole a guest CPU context, where in the case of reading > virtio ring it is from host and it has no guest CPU context. But I think > we can continue the discussion on the list in that thread. > >> >> This is a very technical topic, not sure if the community call will >> be a better place than the mailing list, in particular if no virtio / >> atomic expert developers appears. We'll see :) > > Yes, I had such similar feeling that the problem was not yet blocked by > something that a video call would better help.. > > For example, I still want to double check if that change would work for > your current use case, it will at least verify the thought, no matter if we > want to use it or not. > > Thanks, >
Thanks for your reply. Your change works for the virtio use case. While waiting for further comments, I've also gathered some additional information. Let's continue the discussion on the original thread. -- BillXiang
