On Sun, 2026-08-23 at 21:14 +0800, [email protected] wrote: > The envcfg CBO fields are provided by Zicbom and Zicboz. Keep them > read-only zero when the corresponding extension is absent in all > three > envcfg CSRs. > Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/4225 > > Signed-off-by: wangyang <[email protected]>
Reviewed-by: Alistair Francis <[email protected]> Alistair > --- > target/riscv/tcg/csr.c | 38 ++++++++++++++++++++++++++++++++++---- > 1 file changed, 34 insertions(+), 4 deletions(-) > > diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c > index 7078736..fd00538 100644 > --- a/target/riscv/tcg/csr.c > +++ b/target/riscv/tcg/csr.c > @@ -3212,10 +3212,19 @@ static RISCVException > write_menvcfg(CPURISCVState *env, int csrno, > target_ulong val, uintptr_t ra) > { > const RISCVCPUConfig *cfg = riscv_cpu_cfg(env); > - uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | > - MENVCFG_CBZE; > + uint64_t mask = MENVCFG_FIOM; > bool stce_changed = false; > > + /* CBIE/CBCFE are read-only zero when Zicbom is not implemented. > */ > + if (cfg->ext_zicbom) { > + mask |= MENVCFG_CBIE | MENVCFG_CBCFE; > + } > + > + /* CBZE is read-only zero when Zicboz is not implemented. */ > + if (cfg->ext_zicboz) { > + mask |= MENVCFG_CBZE; > + } > + > if (riscv_cpu_mxl(env) == MXL_RV64) { > mask |= (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) | > (cfg->ext_sstc ? MENVCFG_STCE : 0) | > @@ -3319,8 +3328,19 @@ static RISCVException > read_senvcfg(CPURISCVState *env, int csrno, > static RISCVException write_senvcfg(CPURISCVState *env, int csrno, > target_ulong val, uintptr_t ra) > { > - uint64_t mask = SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | > SENVCFG_CBZE; > + uint64_t mask = SENVCFG_FIOM; > RISCVException ret; > + > + /* CBIE/CBCFE are read-only zero when Zicbom is not implemented. > */ > + if (env_archcpu(env)->cfg.ext_zicbom) { > + mask |= SENVCFG_CBIE | SENVCFG_CBCFE; > + } > + > + /* CBZE is read-only zero when Zicboz is not implemented. */ > + if (env_archcpu(env)->cfg.ext_zicboz) { > + mask |= SENVCFG_CBZE; > + } > + > /* Update PMM field only if the value is valid according to Zjpm > v1.0 */ > if (env_archcpu(env)->cfg.ext_ssnpm && > riscv_cpu_mxl(env) == MXL_RV64 && > @@ -3377,7 +3397,7 @@ static RISCVException > write_henvcfg(CPURISCVState *env, int csrno, > target_ulong val, uintptr_t ra) > { > const RISCVCPUConfig *cfg = riscv_cpu_cfg(env); > - uint64_t mask = HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | > HENVCFG_CBZE; > + uint64_t mask = HENVCFG_FIOM; > RISCVException ret; > bool stce_changed = false; > > @@ -3386,6 +3406,16 @@ static RISCVException > write_henvcfg(CPURISCVState *env, int csrno, > return ret; > } > > + /* CBIE/CBCFE are read-only zero when Zicbom is not implemented. > */ > + if (cfg->ext_zicbom) { > + mask |= HENVCFG_CBIE | HENVCFG_CBCFE; > + } > + > + /* CBZE is read-only zero when Zicboz is not implemented. */ > + if (cfg->ext_zicboz) { > + mask |= HENVCFG_CBZE; > + } > + > if (riscv_cpu_mxl(env) == MXL_RV64) { > mask |= env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | > HENVCFG_ADUE | > HENVCFG_DTE);
