Hi everyone,
In theory we should wait for sdext ("[PATCH v7 0/7] riscv: add initial
sdext support") to land before pushing this board again, but there seems
to be a demand for checking the current state of this work. So here it
is.
The changes from v8 are mostly based on previous work done in the RISC-V
tree in the form of FDT/device helpers, reducing the amount of code
repetition between this board and 'virt'. In v8 this board had 1477
lines and now we're down to 771 lines.
I also squashed the 2 TPM related patches, that were already acked and
reviewed, into the base code. We're now carrying 5 patches instead of
7.
Other minor changes were made based on v8 feedback. They were minor to
a point where I kept the ack from Nutty Liu in patch 3. This means that
we have all patches acked.
Patches based on alistair/riscv-to-apply.next. The series is also
available here:
https://gitlab.com/danielhb/qemu/-/tree/riscv-server-ref_v9
Changes from v8:
- former patch 5 ("hw/riscv/server_platform_ref.c: add platform bus and TPM
support"):
- squashed into patch 3
- former patch 6 ("tests/functional/riscv64: add riscv-server-ref TPM
selftest"):
- squashed into patch 4
- patch 3:
- using decimal instead of hex for RVSERVER_PCIE_IRQ and IOMMU_SYS_IRQ
- updated mc->desc to "RISC-V Server Platform Reference Board v1.0"
- use MachineClass->desc as '/model' in the DT
- v8 link:
https://lore.kernel.org/qemu-devel/[email protected]/
Based-on: <[email protected]>
([PATCH v7 0/7] riscv: add initial sdext support)
Daniel Henrique Barboza (5):
target/riscv/cpu.c: remove 'bare' condition for .profile
target/riscv: add riscv-server-ref CPU
hw/riscv: server platform reference machine
tests/functional/riscv64: add riscv-server-ref tests
docs: add riscv-server-ref.rst
configs/devices/riscv64-softmmu/default.mak | 1 +
docs/system/riscv/riscv-server-ref.rst | 62 ++
docs/system/target-riscv.rst | 1 +
hw/riscv/Kconfig | 16 +
hw/riscv/meson.build | 1 +
hw/riscv/server_platform_ref.c | 771 ++++++++++++++++++++
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 32 +-
tests/functional/riscv64/meson.build | 2 +
tests/functional/riscv64/test_opensbi.py | 4 +
tests/functional/riscv64/test_server_ref.py | 88 +++
11 files changed, 978 insertions(+), 1 deletion(-)
create mode 100644 docs/system/riscv/riscv-server-ref.rst
create mode 100644 hw/riscv/server_platform_ref.c
create mode 100755 tests/functional/riscv64/test_server_ref.py
--
2.43.0
