On 8/20/2026 2:51 PM, Brian Cain wrote: > A Q reg can be built by a vector compare or by vand(Vu, Rt), and > those reach the predicate register through independent code paths. Check > that both select the same byte lanes, so a byte-order mistake in either > one is caught. > > The input alternates every eight lanes: a flatter pattern > stays unchanged when predicate bytes are permuted and hides the bug. > > Signed-off-by: Brian Cain <[email protected]> > --- > tests/tcg/hexagon/hvx_misc.c | 45 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 45 insertions(+) >
Reviewed-by: Pierrick Bouvier <[email protected]>
