On Thu, 2026-09-03 at 15:21 +0930, Joel Stanley wrote: > v2: > https://lore.kernel.org/qemu-riscv/[email protected] > > Changes in v3: > > - Rebase on today's riscv-to-apply.next, fixing conflicts with the > device tree rework > - Take up Phil's suggestion to change @mr to @container in the first > five patches > - Add r-b from Alistair, Daniel, Phil. Thank you! > > Original commit message: > > This addresses the review given by Cedric on v1 of the Atlantis > patches, > where he suggested making the machine a SoC. This is the pattern > followed by the Aspeed ARM machines, where the SoC represents the > modelled hardware, attaching its devices to a memory container, with > the > SoC instantiated by a QEMU machine that provides the memory container > and the machine's RAM. > > Aside from the clean abstraction that this encourages, this pattern > will > be useful in adding other SoCs to the Atlantis machine, such as the > RCPU > (boot microcontroller) and CPL (Cluster Power Logic microcontroller). > > The series converts the RISC-V interrupt controllers to take a > MemoryRegion for mapping themselves, with no change in behaviour for > existing machines, and then cleans up the CPS device to place its > devices in the memory container provided. > > The next few patches clean up the Atlantis machine to make extracting > the SoC device and mapping it in a container relatively > straightforward. > > Joel Stanley (15): > hw/riscv/aia: Take a MemoryRegion for the created devices > hw/intc/riscv_aclint: Take a MemoryRegion for the created devices > hw/intc/riscv_imsic: Take a MemoryRegion for the created device > hw/intc/riscv_aplic: Take a MemoryRegion for the created device > hw/intc/sifive_plic: Take a MemoryRegion for the created device > hw/riscv/cps: Map interrupt controllers in SoC container > hw/riscv/atlantis: Make UART unimp region a SoC device > hw/riscv/atlantis: Remove unused fdt_size > hw/riscv/atlantis: Rename hart array 'soc' to 'cpus' > hw/riscv/atlantis: Rework device tree creation > hw/riscv/atlantis: Use local reference for system memory > hw/riscv/atlantis: Decouple RAM size from MachineState > hw/riscv/atlantis: Make TTAtlantisState own memory containers > hw/riscv/atlantis: Extract an Atlantis SoC device > hw/riscv/atlantis: Map the SoC through a memory container > > Portia Stephens (1): > hw/riscv: Add property to hart array to allow private memory
Thanks! Applied to riscv-to-apply.next Alistair > > hw/riscv/aia.h | 3 +- > include/hw/intc/riscv_aclint.h | 7 +- > include/hw/intc/riscv_aplic.h | 7 +- > include/hw/intc/riscv_imsic.h | 3 +- > include/hw/intc/sifive_plic.h | 4 +- > include/hw/riscv/riscv_hart.h | 2 + > include/hw/riscv/tt_atlantis.h | 32 +++- > hw/intc/riscv_aclint.c | 12 +- > hw/intc/riscv_aplic.c | 10 +- > hw/intc/riscv_imsic.c | 6 +- > hw/intc/sifive_plic.c | 7 +- > hw/riscv/aia.c | 17 +- > hw/riscv/cps.c | 12 +- > hw/riscv/k230.c | 9 +- > hw/riscv/microchip_pfsoc.c | 8 +- > hw/riscv/riscv_hart.c | 8 + > hw/riscv/shakti_c.c | 10 +- > hw/riscv/sifive_e.c | 6 +- > hw/riscv/sifive_u.c | 10 +- > hw/riscv/spike.c | 4 +- > hw/riscv/tt_atlantis.c | 280 +++++++++++++++++++++---------- > -- > hw/riscv/virt.c | 21 ++- > hw/riscv/xiangshan_kmh.c | 17 +- > 23 files changed, 326 insertions(+), 169 deletions(-)
