The ccmov, pref, lwp, and swp encodings are classified as RV64-only in xmips.decode, but their translators only check the corresponding extension property. With the property enabled, RV32 can therefore retire these encodings. Apply the same XLEN check already used by the ldp and sdp translators.
Tested with the 12-case RV32/RV64 linux-user witness and control matrix on a clean patched QEMU build. Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/4404 Signed-off-by: wangyang <[email protected]> --- target/riscv/tcg/insn_trans/trans_xmips.c.inc | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/riscv/tcg/insn_trans/trans_xmips.c.inc b/target/riscv/tcg/insn_trans/trans_xmips.c.inc index 1b9993a9b0..37c8933221 100644 --- a/target/riscv/tcg/insn_trans/trans_xmips.c.inc +++ b/target/riscv/tcg/insn_trans/trans_xmips.c.inc @@ -31,6 +31,7 @@ static bool trans_ccmov(DisasContext *ctx, arg_ccmov *a) { REQUIRE_XMIPSCMOV(ctx); + REQUIRE_64_OR_128BIT(ctx); TCGv zero, source1, source2, source3; zero = tcg_constant_tl(0); @@ -74,6 +75,7 @@ static bool trans_lwp(DisasContext *ctx, arg_lwp *a) MemOp memop = MO_SL | ctx->mo_endianness; REQUIRE_XMIPSLSP(ctx); + REQUIRE_64_OR_128BIT(ctx); TCGv src = get_gpr(ctx, a->rs1, EXT_NONE); TCGv dest0 = dest_gpr(ctx, a->rd); @@ -119,6 +121,7 @@ static bool trans_swp(DisasContext *ctx, arg_swp *a) MemOp memop = MO_SL | ctx->mo_endianness; REQUIRE_XMIPSLSP(ctx); + REQUIRE_64_OR_128BIT(ctx); TCGv src = get_gpr(ctx, a->rs1, EXT_NONE); TCGv data0 = get_gpr(ctx, a->rs2, EXT_NONE); @@ -138,6 +138,7 @@ static bool trans_pref(DisasContext *ctx, arg_pref *a) static bool trans_pref(DisasContext *ctx, arg_pref *a) { REQUIRE_XMIPSCBOP(ctx); + REQUIRE_64_OR_128BIT(ctx); /* Nop */ return true; -- 2.55.0.windows.2
