On Fri, 4 Sept 2026 at 06:20, <[email protected]> wrote: > > From: Alistair Francis <[email protected]> > > The following changes since commit 99e54ab5e7a6efc945af6d5661842155d1f3fc7a: > > Merge tag 'hw-misc-20260903' of https://github.com/philmd/qemu into staging > (2026-09-03 16:43:24 +0100) > > are available in the Git repository at: > > https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20260904 > > for you to fetch changes up to b23a62773a7856299cbb3782e64968b6a92c792f: > > hw/riscv/atlantis: Map the SoC through a memory container (2026-09-04 > 10:30:14 +1000) > > ---------------------------------------------------------------- > RISC-V PR for 11.2 > > * Add initial sdext support > * Make RISCVBootInfo const where possible > * Use hwaddr for virt IMSIC device tree address > * Avoid unnecessary removal of test scratch files > * Document Atlantis QEMU-only I2C device tree nodes > * Make s-mode IMSIC stride explicit > * Correct dasm for cbo and lq > * Add tests for rv128 [ms]status > * Code duplication work in preperation for riscv-server-ref > * Fix user option hash table leaks > * Preserve vl on element-zero fault > * Prevent abrupt abortion on unassigned value write to tdata > * Socify Atlantis > > ----------------------------------------------------------------
Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/11.2 for any user-visible changes. -- PMM
