PolarFire SoC has a 2MiB L2 cache, so the maximum mapped size of L2LIM should be set to 2MiB too.
Signed-off-by: Bin Meng <[email protected]> Reviewed-by: Chao Liu <[email protected]> Acked-by: Alistair Francis <[email protected]> --- (no changes since v1) hw/riscv/microchip_pfsoc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index edd29626fa..cfba2990b6 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -95,7 +95,7 @@ static const MemMapEntry microchip_pfsoc_memmap[] = { [MICROCHIP_PFSOC_CLINT] = { 0x2000000, 0x10000 }, [MICROCHIP_PFSOC_L2CC] = { 0x2010000, 0x1000 }, [MICROCHIP_PFSOC_DMA] = { 0x3000000, 0x100000 }, - [MICROCHIP_PFSOC_L2LIM] = { 0x8000000, 0x2000000 }, + [MICROCHIP_PFSOC_L2LIM] = { 0x8000000, 0x200000 }, [MICROCHIP_PFSOC_PLIC] = { 0xc000000, 0x4000000 }, [MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 }, [MICROCHIP_PFSOC_WDOG0] = { 0x20001000, 0x1000 }, -- 2.53.0
