Greetings, The latest RISC-V PR merged in trunk introduced changes that conflicts with the v9 version. This version is a trivial rebase on top of it.
No other changes made. Patches based on master. All patches acked. Please bear in mind that we need [PATCH v7 0/7] riscv: add initial sdext support To land before this series. Changes from v9: - fixed conflicts after changes in QAPI and aia/mtimer APIs that landed in master. - v9 link: https://lore.kernel.org/qemu-devel/[email protected]/ Based-on: <[email protected]> ([PATCH v7 0/7] riscv: add initial sdext support) Daniel Henrique Barboza (5): target/riscv/cpu.c: remove 'bare' condition for .profile target/riscv: add riscv-server-ref CPU hw/riscv: server platform reference machine tests/functional/riscv64: add riscv-server-ref tests docs: add riscv-server-ref.rst configs/devices/riscv64-softmmu/default.mak | 1 + docs/system/riscv/riscv-server-ref.rst | 62 ++ docs/system/target-riscv.rst | 1 + hw/riscv/Kconfig | 16 + hw/riscv/meson.build | 1 + hw/riscv/server_platform_ref.c | 769 ++++++++++++++++++++ target/riscv/cpu-qom.h | 1 + target/riscv/cpu.c | 32 +- tests/functional/riscv64/meson.build | 2 + tests/functional/riscv64/test_opensbi.py | 4 + tests/functional/riscv64/test_server_ref.py | 88 +++ 11 files changed, 976 insertions(+), 1 deletion(-) create mode 100644 docs/system/riscv/riscv-server-ref.rst create mode 100644 hw/riscv/server_platform_ref.c create mode 100755 tests/functional/riscv64/test_server_ref.py -- 2.43.0
