Greetings, This version is a simple rebase with master, where a trivial conflict with tests/tcg/riscv64/Makefile.softmmu-target was solved, and with my S-o-Bs on patches 1-6.
No other changes made. Patches based on master. Changes from v7: - Added my S-o-B in patches 1-6 - Patch 7: - fixed conflict with Makefile.softmmu-target - v7 link: https://lore.kernel.org/qemu-devel/[email protected]/ Chao Liu (6): target/riscv: add sdext debug CSRs state target/riscv: add sdext Debug Mode helpers target/riscv: add dret instruction target/riscv: add sdext enter Debug Mode on ebreak target/riscv: add sdext single-step support target/riscv: add sdtrig trigger action=debug mode Daniel Henrique Barboza (1): tests/tcg/riscv64: add sdext "not on Debug mode" sigill tests include/exec/translation-block.h | 4 +- target/riscv/cpu.c | 7 + target/riscv/cpu.h | 9 ++ target/riscv/cpu_bits.h | 33 +++++ target/riscv/cpu_cfg_fields.h.inc | 1 + target/riscv/helper.h | 3 + target/riscv/insn32.decode | 1 + target/riscv/machine.c | 20 +++ target/riscv/tcg/cpu_helper.c | 91 +++++++++++++ target/riscv/tcg/csr.c | 126 ++++++++++++++++++ target/riscv/tcg/debug.c | 59 +++++++- .../tcg/insn_trans/trans_privileged.c.inc | 24 ++++ target/riscv/tcg/op_helper.c | 70 ++++++++++ target/riscv/tcg/tcg-cpu.c | 19 +++ target/riscv/tcg/translate.c | 15 ++- tests/tcg/riscv64/Makefile.softmmu-target | 5 + tests/tcg/riscv64/test-sdext-sigill.S | 83 ++++++++++++ 17 files changed, 564 insertions(+), 6 deletions(-) create mode 100644 tests/tcg/riscv64/test-sdext-sigill.S -- 2.43.0
