Some banked AArch32 cpregs set up a resetfn of arm_cp_reset_ignore. This is presumably in an expectation that some other AArch64 register will handle resetting the underlying state. However this isn't true for some of them:
* TPIDRURO's S bank is in cp15.tpidruro_s and this isn't shared with any AArch64 register * TPIDRURW's S bank similarly is in cp15.tpidrurw_s, not shared with any AArch64 register Remove the use of arm_cp_reset_ignore here; this means that the state for the NS versions of these registers will be reset twice, but that is fine because it will always be to the same value (and the cp_reg_check_reset() code will assert if we introduce a bug where the AArch64 and AArch32 regs disagree about the reset value). For the MAIR0 and MAIR1 banked registers, doing nothing on reset is OK because they are backed by state that is always covered by the MAIR_EL1 and MAIR_EL3 AArch64 registers that will always be present if the AArch32 registers are. But it's not consistent with how we handle all the other banked regs, so drop it here too. Again, the cp_reg_check_reset() checks will catch any mismatches in what the reset value should be. The lack of reset-to-zero for the S banked versions of TPIDRURO and TPIDRURW is very unlikely to have had any guest visible consquences, because these registers are architecturally UNKNOWN at reset and so guest code should be initializing them itself regardless. Signed-off-by: Peter Maydell <[email protected]> --- target/arm/helper.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 1b024adc703..f8185b201be 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1072,14 +1072,12 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW, .accessfn = access_tvm_trvm, .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair0_s), - offsetof(CPUARMState, cp15.mair0_ns) }, - .resetfn = arm_cp_reset_ignore }, + offsetof(CPUARMState, cp15.mair0_ns) }, }, { .name = "MAIR1", .state = ARM_CP_STATE_AA32, .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW, .accessfn = access_tvm_trvm, .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair1_s), - offsetof(CPUARMState, cp15.mair1_ns) }, - .resetfn = arm_cp_reset_ignore }, + offsetof(CPUARMState, cp15.mair1_ns) }, }, { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0, .fgt = FGT_ISR_EL1, @@ -1136,8 +1134,7 @@ static const ARMCPRegInfo v6k_cp_reginfo[] = { .access = PL0_RW, .fgt = FGT_TPIDR_EL0, .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s), - offsetoflow32(CPUARMState, cp15.tpidrurw_ns) }, - .resetfn = arm_cp_reset_ignore }, + offsetoflow32(CPUARMState, cp15.tpidrurw_ns) }, }, { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0, .access = PL0_R | PL1_W, @@ -1148,8 +1145,7 @@ static const ARMCPRegInfo v6k_cp_reginfo[] = { .access = PL0_R | PL1_W, .fgt = FGT_TPIDRRO_EL0, .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s), - offsetoflow32(CPUARMState, cp15.tpidruro_ns) }, - .resetfn = arm_cp_reset_ignore }, + offsetoflow32(CPUARMState, cp15.tpidruro_ns) }, }, { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0, .access = PL1_RW, -- 2.43.0
