On Fri, 4 Sept 2026 at 02:30, Max Chou <[email protected]> wrote: > > According to the RISC-V unpriviledge spec, > "vset{i}vl{i} and whole register loads and stores do not depend upon > vtype." > The whole-register vector move instructions reuqire legal vtype that > trap when VILL is set. > > The tcg_out_mov in tcg/riscv64 missed the vtype setup before emitting the > OPC_VMVNR_V. > > Fixes: d4be6ee1111 ("tcg/riscv: Implement vector mov/dup{m/i}") > Signed-off-by: Max Chou <[email protected]>
Reviewed-by: Joel Stanley <[email protected]> Thanks! I had the same patch in my tree. I hit a crash running qemu-x86_64 on top of qemu-system-riscv64 -cpu rva23u64. Notably the spacemit K3 doesn't crash, but other (stricter) implementations will. Cheers, Joel
