Re: [RFC v5 26/28] hw/arm/smmuv3: Initialize the secure register bank

[Tao Tang]

On 8/31/2026 4:37 PM, Eric Auger wrote:

On 8/13/26 6:26 PM, Tao Tang wrote:
Initialize the secure register bank (SMMU_SEC_SID_S) with sane default
values during the SMMU's reset sequence.

This change ensures that key fields, such as the secure ID registers,
GBPA reset value, and queue entry sizes, are set to a known-good state.
The SECURE_IMPL attribute of the S_IDR1 register will be introduced
later via device properties.
what about SEL2 then? Do you eventually target this in this series?

Hi Eric,

We won't implement SEL2 in this series as mentioned in previous mail. 
The last patch is only a temporary one for Hafnium bring-up.


This is a necessary step to prevent undefined behavior when secure SMMU
features are subsequently enabled and used by software.

Signed-off-by: Tao Tang <tangtao1...@phytium.com.cn>
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
---
  hw/arm/smmuv3.c | 29 ++++++++++++++++++++++++++++-
  1 file changed, 28 insertions(+), 1 deletion(-)

diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index 2375b7a17a0..7e7376c65e2 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
@@ -293,6 +293,7 @@ void smmuv3_record_event(SMMUv3State *s, SMMUEventInfo 
*info)
  static void smmuv3_init_id_regs(SMMUv3State *s)
  {
      SMMUv3RegBank *bank = smmuv3_bank(s, SMMU_SEC_SID_NS);
+    SMMUv3RegBank *sbank = smmuv3_bank(s, SMMU_SEC_SID_S);
  
      /* Based on sys property, the stages supported in smmu will be advertised.*/
      if (s->stage && !strcmp("2", s->stage)) {
@@ -339,7 +340,14 @@ static void smmuv3_init_id_regs(SMMUv3State *s)
      bank->idr[5] = FIELD_DP32(bank->idr[5], IDR5, GRAN4K, 1);
      bank->idr[5] = FIELD_DP32(bank->idr[5], IDR5, GRAN16K, 1);
      bank->idr[5] = FIELD_DP32(bank->idr[5], IDR5, GRAN64K, 1);
-    s->aidr = 0x1;
+
+    /* Initialize Secure bank */
+    memset(sbank->idr, 0, sizeof(sbank->idr));
+    /* No stall */
+    sbank->idr[0] = FIELD_DP32(sbank->idr[0], S_IDR0, STALL_MODEL, 1);
+
+    sbank->idr[1] = FIELD_DP32(sbank->idr[1], S_IDR1, S_SIDSIZE,
what about S_IDR3.SAMS?


SAMS is already 0 through the memset. Since it is RES0 when ATS is not 
advertised, could we leave it as is in that configuration?


Best regards,

Tao

+                               SMMU_IDR1_SIDSIZE);
      smmuv3_accel_idr_override(s);
  }