On 8/31/2026 1:23 PM, Eric Auger wrote:
Hi Tao,
On 8/13/26 6:26 PM, Tao Tang wrote:
Implement read/write handlers for the SMMU_S_INIT secure-only register.
Writing INV_ALL provides a mechanism for software to perform a global
invalidation of ALL caches within the SMMU, including IOTLBs and
configuration caches across all security states.
The MMIO dispatcher decodes the target register bank from the offset and
normalizes Secure-window offsets by subtracting SMMU_SECURE_REG_START
before switching on the bank-local offset. S_INIT is a Secure-only
register and its A_S_INIT constant is an absolute Secure-window offset,
so the handler matches it using A_S_INIT - SMMU_SECURE_REG_START and
rejects accesses through Non-secure banks.
Signed-off-by: Tao Tang <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
---
hw/arm/smmuv3.c | 43 +++++++++++++++++++++++++++++++++++++++++++
hw/arm/trace-events | 1 +
2 files changed, 44 insertions(+)
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index d69fc0898af..dc3fa618883 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
@@ -393,6 +393,21 @@ static int smmu_get_ste(SMMUv3State *s, dma_addr_t addr,
STE *buf,
}
+static void smmuv3_invalidate_all_caches(SMMUv3State *s)
+{
+ SMMUState *bs = &s->smmu_state;
+ trace_smmuv3_invalidate_all_caches();
+
+ /* Clear all cached configs including STE and CD */
+ if (bs->configs) {
+ g_hash_table_remove_all(bs->configs);
+ }
+
+ /* Invalidate all SMMU IOTLB entries */
+ smmu_inv_notifiers_all(&s->smmu_state);
+ smmu_iotlb_inv_all(bs);
+}
+
static SMMUTranslationStatus smmuv3_do_translate(SMMUv3State *s, hwaddr addr,
SMMUTransCfg *cfg,
SMMUEventInfo *event,
@@ -2206,7 +2221,29 @@ static MemTxResult smmu_writel(SMMUv3State *s, hwaddr
offset,
bank->eventq_irq_cfg2 = data;
break;
+ case A_S_INIT - SMMU_SECURE_REG_START:
+ if (reg_sec_sid != SMMU_SEC_SID_S) {
+ goto unhandled;
+ }
+ if (data & R_S_INIT_INV_ALL_MASK) {
+ /*
+ * If SMMU_ROOT_CR0.GPCEN == 0, a write of 1 to INV_ALL when any
+ * SMMU_(*_)CR0.SMMUEN == 1, .... , is CONSTRAINED UNPREDICTABLE
+ * according to (IHI 0070G.b) 6.3.62 SMMU_S_INIT, Page 465.
+ */
+ if (!smmuv3_smmu_disabled_stable(s, SMMU_SEC_SID_NS) ||
+ !smmuv3_smmu_disabled_stable(s, SMMU_SEC_SID_S)) {
+ /* CONSTRAINED UNPREDICTABLE behavior: Ignore this write */
+ qemu_log_mask(LOG_GUEST_ERROR, "S_INIT write ignored: "
+ "(S_)CR0.SMMUEN or (S_)CR0ACK.SMMUEN is set\n");
+ return MEMTX_OK;
+ }
shall we really bother: I read:
"
If SMMU_ROOT_CR0.GPCEN == 0, a write of 1 to INV_ALL when any
SMMU_(*_)CR0.SMMUEN == 1,
or an Update of any SMMUEN to 1 is in progress, or
SMMU_ROOT_CR0.ACCESSEN == 1, or an Update of
ACCESSEN to 1 is in progress, is CONSTRAINED UNPREDICTABLE and has one
of the following behaviors:
• The write is IGNORED.
• The invalidation operation occurs and completes, with INV_ALL reset to
0 on completion.
"
So the second behavior would let us simplify the code, no?
Hi Eric,
Yes, the second permitted behavior lets us remove the SMMUEN checks and
complete the invalidation synchronously. I'll simplify this in v6.
By the way where is GPCEN checked?
GPCEN is not currently checked because this SMMU model does not
implement the Root programming interface or granule protection checks.
I'll clarify that limitation. When that support is added, INV_ALL must
have no effect while GPCEN is set.
Best regards
Tao
Eric
+ smmuv3_invalidate_all_caches(s);
+ }
+ /* Synchronous emulation: invalidation completed instantly. */
+ break;
default:
