Hi,
On 9/8/2026 7:28 PM, Christian S. Lima wrote:
The risc v privileged specification requires hinval.vvma, hinval.gvma,
sfence.w.inval and sfence.inval.ir should raise a virtual instruction
exception when executed in the vu-mode. This patch add the check to
raise the virtual instruction exception when is in the vu-mode.
Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3621
Signed-off-by: Christian S. Lima <[email protected]>
---
target/riscv/tcg/insn_trans/trans_svinval.c.inc | 4 ++++
target/riscv/tcg/insn_trans/trans_xthead.c.inc | 13 ++++++++-----
2 files changed, 12 insertions(+), 5 deletions(-)
diff --git a/target/riscv/tcg/insn_trans/trans_svinval.c.inc
b/target/riscv/tcg/insn_trans/trans_svinval.c.inc
index 4614c1489c..251d9c5815 100644
--- a/target/riscv/tcg/insn_trans/trans_svinval.c.inc
+++ b/target/riscv/tcg/insn_trans/trans_svinval.c.inc
@@ -25,8 +25,12 @@
/* Test if priv level is M or S. */
#define REQUIRE_PRIV_MS(ctx) do { \
if (ctx->priv == PRV_U) { \
+ if (ctx->virt_enabled) { \
+ ctx->virt_inst_excp = true; \
+ } \
return false; \
} \
+ return true; \
We can't 'return true' in this macro. This is a "return false if wrong,
otherwise
do nothing" macro that this file uses. It works like REQUIRE_SVINVAL():
#define REQUIRE_SVINVAL(ctx) do { \
if (!ctx->cfg_ptr->ext_svinval) { \
return false; \
} \
} while (0)
If you look at trans_sinval_vma(), adding a 'return true' in REQUIRE_PRIV_MS()
will
cause an early exit right after the macro, short-circuiting everything after it:
static bool trans_sinval_vma(DisasContext *ctx, arg_sinval_vma *a)
{
REQUIRE_SVINVAL(ctx);
/* Do the same as sfence.vma currently */
REQUIRE_EXT(ctx, RVS);
REQUIRE_PRIV_MS(ctx); <===========
#ifndef CONFIG_USER_ONLY
decode_save_opc(ctx, 0);
gen_helper_tlb_flush(tcg_env);
return true;
#endif
return false;
Same thing with REQUIRE_PRIV_MS(ctx) in trans_xthead.c.inc down below: we can't
add a
'return true' in it too.
Cheers,
Daniel
} while (0)
static bool trans_sinval_vma(DisasContext *ctx, arg_sinval_vma *a)
diff --git a/target/riscv/tcg/insn_trans/trans_xthead.c.inc
b/target/riscv/tcg/insn_trans/trans_xthead.c.inc
index f4e3051000..c00b007895 100644
--- a/target/riscv/tcg/insn_trans/trans_xthead.c.inc
+++ b/target/riscv/tcg/insn_trans/trans_xthead.c.inc
@@ -267,11 +267,14 @@ static bool trans_th_tst(DisasContext *ctx, arg_th_tst *a)
#define REQUIRE_PRIV_MSU(ctx)
/* Test if priv level is M or S. */
-#define REQUIRE_PRIV_MS(ctx) \
-do { \
- if (ctx->priv == PRV_U) { \
- return false; \
- } \
+#define REQUIRE_PRIV_MS(ctx) do { \
+ if (ctx->priv == PRV_U) { \
+ if (ctx->virt_enabled) { \
+ ctx->virt_inst_excp = true; \
+ } \
+ return false; \
+ } \
+ return true; \
} while (0)
#define NOP_PRIVCHECK(insn, extcheck, privcheck) \
