Reset enters M-mode without clearing virt_enabled, leaving an invalid M-mode, V=1 state after a reset from virtual mode. Clear virt_enabled alongside the privilege reset.
Signed-off-by: TANG Tiancheng <[email protected]> --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5fff9d745e9b36d9cbd30f166ec91b5165e5f497..f60d7cca1e2f0008b09b1055c5cdeed3ec4ad1d3 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -980,6 +980,7 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type) #ifndef CONFIG_USER_ONLY env->misa_mxl = mcc->def->misa_mxl_max; env->priv = PRV_M; + env->virt_enabled = false; env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); if (env->misa_mxl > MXL_RV32) { /* -- 2.43.0
