This series fixes RISC-V TCG PMU accounting, overflow notification, and migration. It is based on v2 of Zephyr Li's "target/riscv: fix RV32 fixed counter accesses" [1], which is not included here.
The patches allow multiple HPM counters to select the same event and preserve counts across selector, privilege-filter, and inhibit writes. They use consistent cycle/instruction sources and compute the shared overflow deadline from all eligible counters. Timer callbacks queue checks on the owner vCPU instead of racing MTTCG execution. Migration saves counter values including pending increments and restores destination-local source baselines, event mappings, and overflow scheduling. A new cpu/pmu-fixed subsection carries mcyclecfg/minstretcfg and identifies this format. All TCG CPUs require the subsection; loading older TCG streams without it is rejected. Source and destination still need compatible CPU configurations. KVM PMU migration is unchanged. The reset changes preserve the final counts in the old privilege/V mode before entering M-mode with V=0. TCG tests cover RV32/RV64 counter accesses, delegated registers, selector and filter changes, multiple counters per event, overflow notification with and without Sscofpmf, instruction exceptions, and reset. The RV32 HPM tests also cover full-width accesses through the shared counter path. [1] https://lore.kernel.org/qemu-devel/[email protected]/ Based-on: <[email protected]> Signed-off-by: TANG Tiancheng <[email protected]> --- Changes in v2: - Rebase on current master and Zephyr Li's RV32 fix v2. - Register the system TCG tests with Meson and use -bios loading. - Merge smcdeleg-counter-rv32.S and smcdeleg-event-rv32.S into smcdeleg-rv32.S (patch 6). - Use CSR names or local CSR-number macros in tests. - Use UINT32_MAX for delegated high-half write-mask checks (patch 6). The caller already requires XLEN=32. - Link to v1: https://lore.kernel.org/qemu-devel/20260907-riscv-pmu-correctness-v1-0-5f1f41458...@linux.alibaba.com --- TANG Tiancheng (14): target/riscv: Preserve PMU state across event selector writes target/riscv: Support multiple counters per PMU event target/riscv: Use VM-elapsed sources for fixed PMU events target/riscv: Preserve MINH on delegated config reads target/riscv: Preserve minstretcfgh on RV32 minstretcfg writes target/riscv: Fix RV32 accesses to delegated PMU registers target/riscv: Preserve fixed counters across PMU state changes target/riscv: Require Sscofpmf for non-fixed event overflow target/riscv: Rebuild fixed-event PMU overflow deadlines target/riscv: Apply minstret exception accounting to HPM counters target/riscv: Process PMU timer expiry on the owner vCPU target/riscv: Migrate fixed PMU counter state target/riscv: Clear virtualization mode on reset target/riscv: Preserve fixed PMU state across reset system/cpu-timers.c | 4 +- system/cpus.c | 6 +- target/riscv/cpu.c | 17 + target/riscv/cpu.h | 14 +- target/riscv/machine.c | 92 +++- target/riscv/tcg/cpu_helper.c | 2 + target/riscv/tcg/csr.c | 278 +++------- target/riscv/tcg/pmu.c | 793 +++++++++++++++++++--------- target/riscv/tcg/pmu.h | 29 +- target/riscv/tcg/tcg-cpu.c | 10 + tests/tcg/riscv32/pmu-fixed-rv32.S | 90 ++++ tests/tcg/riscv32/pmu-minstretcfg-rv32.S | 52 ++ tests/tcg/riscv32/smcdeleg-minh-rv32.S | 78 +++ tests/tcg/riscv32/smcdeleg-rv32.S | 115 ++++ tests/tcg/riscv32/sscofpmf-event-rv32.S | 99 ++++ tests/tcg/riscv32/system/meson.build | 35 ++ tests/tcg/riscv64/pmu-cycle-controls.S | 107 ++++ tests/tcg/riscv64/pmu-lpad.S | 72 +++ tests/tcg/riscv64/pmu-reset-vs.S | 105 ++++ tests/tcg/riscv64/smcdeleg-minh.S | 78 +++ tests/tcg/riscv64/smcdeleg-sxl32.S | 233 ++++++++ tests/tcg/riscv64/sscofpmf-cycle-overflow.S | 58 ++ tests/tcg/riscv64/sscofpmf-event-overflow.S | 103 ++++ tests/tcg/riscv64/sscofpmf-overflow.S | 134 +++++ tests/tcg/riscv64/system/meson.build | 88 +++ tests/tcg/riscv64/test-minstret-ecall.S | 26 + 26 files changed, 2252 insertions(+), 466 deletions(-) --- base-commit: 1df256f5968e9f7c3c4533a1383b071c044a36d6 change-id: 20260827-riscv-pmu-correctness-fa880fd9c48d prerequisite-message-id: <[email protected]> prerequisite-patch-id: f7a8b2a8cc67f360d6abb1adf002b000e7b2eb4d Best regards, -- TANG Tiancheng <[email protected]>
