Currently, we check for register multiwrites during packet decode. The
downside of this approach is that it only checks a single destination
register for each instruction. During analyze_packet, we can check
for more than one write per instruction. Further, we can check for
different types of registers. This series adds checks for HVX
v-registers and q-registers.
Note that multiple writes to a predicate register are allowed on Hexagon.
Changes in v2
- Rebase against latest sources, including Hexagon system mode
- Add checks for multiple writes to system registers
Taylor Simpson (10):
Hexagon (target/hexagon) Move code out of gen_start_packet
Hexagon (target/hexagon) Check for GPR multiwrite in analyze_packet
Hexagon (tests/tcg/hexagon) Add tests for multi-destination
instructions
Hexagon (target/hexagon) Check for vreg multiwrite in analyze_packet
Hexagon (tests/tcg/hexagon) Add tests for vreg multiple writes
Hexagon (target/hexagon) Check for qreg multiwrite in analyze_packet
Hexagon (tests/tcg/hexagon) Add tests for qreg multiple writes
Hexagon (target/hexagon) Check for greg multiwrite in analyze_packet
Hexagon (target/hexagon) Check for sreg multiwrite in analyze_packet
Hexagon (target/hexagon) Remove old way of detecting register
multiwrites
target/hexagon/insn.h | 4 -
target/hexagon/translate.h | 47 ++++++++--
target/hexagon/decode.c | 54 ------------
target/hexagon/translate.c | 88 ++++++++++++++-----
tests/tcg/hexagon/multiple-writes.c | 129 ++++++++++++++++++++++++++++
target/hexagon/gen_trans_funcs.py | 10 ---
tests/tcg/hexagon/meson.build | 2 +-
7 files changed, 239 insertions(+), 95 deletions(-)
--
2.43.0
