Hi,
> The risc v privileged specification requires hinval.vvma, hinval.gvma, > sfence.w.inval and sfence.inval.ir should raise a virtual instruction > exception when executed in the vu-mode. This patch add the check to > raise the virtual instruction exception when is in the vu-mode. > > changes in v2: > - Remove the wrong `return true;` from macro > > Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3621 > > Signed-off-by: Christian S. Lima <[email protected]> > --- > target/riscv/tcg/insn_trans/trans_svinval.c.inc | 3 +++ > target/riscv/tcg/insn_trans/trans_xthead.c.inc | 12 +++++++----- > 2 files changed, 10 insertions(+), 5 deletions(-) > > diff --git a/target/riscv/tcg/insn_trans/trans_svinval.c.inc > b/target/riscv/tcg/insn_trans/trans_svinval.c.inc > index 4614c1489c..5b1172672e 100644 > --- a/target/riscv/tcg/insn_trans/trans_svinval.c.inc > +++ b/target/riscv/tcg/insn_trans/trans_svinval.c.inc > @@ -25,6 +25,9 @@ > /* Test if priv level is M or S. */ > #define REQUIRE_PRIV_MS(ctx) do { \ > if (ctx->priv == PRV_U) { \ > + if (ctx->virt_enabled) { \ > + ctx->virt_inst_excp = true \ I missed a `;` here and below, should I resend a v3? > + } \ > return false; \ > } \ > } while (0) > diff --git a/target/riscv/tcg/insn_trans/trans_xthead.c.inc > b/target/riscv/tcg/insn_trans/trans_xthead.c.inc > index f4e3051000..4bf6594747 100644 > --- a/target/riscv/tcg/insn_trans/trans_xthead.c.inc > +++ b/target/riscv/tcg/insn_trans/trans_xthead.c.inc > @@ -267,11 +267,13 @@ static bool trans_th_tst(DisasContext *ctx, arg_th_tst > *a) > #define REQUIRE_PRIV_MSU(ctx) > > /* Test if priv level is M or S. */ > -#define REQUIRE_PRIV_MS(ctx) \ > -do { \ > - if (ctx->priv == PRV_U) { \ > - return false; \ > - } \ > +#define REQUIRE_PRIV_MS(ctx) do { \ > + if (ctx->priv == PRV_U) { \ > + if (ctx->virt_enabled) { \ > + ctx->virt_inst_excp = true \ > + } \ > + return false; \ > + } \ > } while (0) > > #define NOP_PRIVCHECK(insn, extcheck, privcheck) \ > -- > 2.55.0 > > Thanks, Christian
