Signed-off-by: Richard Henderson <[email protected]>
---
include/tcg/tcg-op-common.h | 2 -
include/tcg/tcg-op-def2.h.inc | 1 +
tcg/tcg-op.c | 90 ++++++++++++-----------------------
3 files changed, 31 insertions(+), 62 deletions(-)
diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h
index ebc0f1714f3..3335e127083 100644
--- a/include/tcg/tcg-op-common.h
+++ b/include/tcg/tcg-op-common.h
@@ -121,7 +121,6 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned meminfo);
/* 32 bit ops */
-void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
@@ -209,7 +208,6 @@ void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg);
/* 64 bit ops */
-void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
diff --git a/include/tcg/tcg-op-def2.h.inc b/include/tcg/tcg-op-def2.h.inc
index 0a17ebf5030..898b77b00c2 100644
--- a/include/tcg/tcg-op-def2.h.inc
+++ b/include/tcg/tcg-op-def2.h.inc
@@ -6,6 +6,7 @@ DEF_RIR(subfi)
DEF_RR(mov)
DEF_RR(neg)
DEF_RRI(addi)
+DEF_RRI(andi)
DEF_RRI(sari)
DEF_RRI(shli)
DEF_RRI(shri)
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index 5936ac43afe..c3e897d479e 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -115,6 +115,12 @@ static TCGOp *gen_op_ttt(TCGOpcode opc, TCGType type,
return tcg_gen_op3(opc, type, temp_arg(t0), temp_arg(t1), temp_arg(t2));
}
+static TCGOp *gen_op_ttii(TCGOpcode opc, TCGType type,
+ TCGTemp *t0, TCGTemp *t1, TCGArg a2, TCGArg a3)
+{
+ return tcg_gen_op4(opc, type, temp_arg(t0), temp_arg(t1), a2, a3);
+}
+
/*
* With CONFIG_DEBUG_TCG, tcgv_*_tmp via tcgv_*_arg, is an out-of-line
* assertion check. Force tail calls to avoid too much code expansion.
@@ -372,6 +378,30 @@ static void gen_and(TCGType type, TCGTemp *dst, TCGTemp
*src1, TCGTemp *src2)
gen_op_ttt(INDEX_op_and, type, dst, src1, src2);
}
+static void gen_andi(TCGType type, TCGTemp *dst, TCGTemp *src1, int64_t src2)
+{
+ if (src2 == 0) {
+ gen_movi(type, dst, 0);
+ } else if (src2 == -1) {
+ gen_mov(type, dst, src1);
+ } else {
+ /*
+ * Canonicalize on extract, if valid. This aids x86 with its
+ * 2 operand MOVZBL and 2 operand AND, selecting the TCGOpcode
+ * which does not require matching operands. Other backends can
+ * trivially expand the extract to AND during code generation.
+ */
+ if (is_power_of_2(src2 + 1)) {
+ unsigned len = cto64(src2);
+ if (TCG_TARGET_extract_valid(type, 0, len)) {
+ gen_op_ttii(INDEX_op_extract, type, dst, src1, 0, len);
+ return;
+ }
+ }
+ gen_and(type, dst, src1, tcg_constant_internal(type, src2));
+ }
+}
+
static void gen_discard(TCGType type, TCGTemp *src)
{
tcg_gen_op1(INDEX_op_discard, type, temp_arg(src));
@@ -512,36 +542,6 @@ static void gen_xor(TCGType type, TCGTemp *dst, TCGTemp
*src1, TCGTemp *src2)
/* 32 bit ops */
-void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
-{
- /* Some cases can be optimized here. */
- switch (arg2) {
- case 0:
- tcg_gen_movi_i32(ret, 0);
- return;
- case -1:
- tcg_gen_mov_i32(ret, arg1);
- return;
- default:
- /*
- * Canonicalize on extract, if valid. This aids x86 with its
- * 2 operand MOVZBL and 2 operand AND, selecting the TCGOpcode
- * which does not require matching operands. Other backends can
- * trivially expand the extract to AND during code generation.
- */
- if (!(arg2 & (arg2 + 1))) {
- unsigned len = ctz32(~arg2);
- if (TCG_TARGET_extract_valid(TCG_TYPE_I32, 0, len)) {
- tcg_gen_extract_i32(ret, arg1, 0, len);
- return;
- }
- }
- break;
- }
-
- tcg_gen_and_i32(ret, arg1, tcg_constant_i32(arg2));
-}
-
void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
{
/* Some cases can be optimized here. */
@@ -1520,36 +1520,6 @@ void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2,
tcg_target_long offset)
tcg_gen_ldst_op_i64(INDEX_op_st, arg1, arg2, offset);
}
-void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
-{
- /* Some cases can be optimized here. */
- switch (arg2) {
- case 0:
- tcg_gen_movi_i64(ret, 0);
- return;
- case -1:
- tcg_gen_mov_i64(ret, arg1);
- return;
- default:
- /*
- * Canonicalize on extract, if valid. This aids x86 with its
- * 2 operand MOVZBL and 2 operand AND, selecting the TCGOpcode
- * which does not require matching operands. Other backends can
- * trivially expand the extract to AND during code generation.
- */
- if (!(arg2 & (arg2 + 1))) {
- unsigned len = ctz64(~arg2);
- if (TCG_TARGET_extract_valid(TCG_TYPE_I64, 0, len)) {
- tcg_gen_extract_i64(ret, arg1, 0, len);
- return;
- }
- }
- break;
- }
-
- tcg_gen_and_i64(ret, arg1, tcg_constant_i64(arg2));
-}
-
void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
{
/* Some cases can be optimized here. */
--
2.53.0
