From: vpyr <[email protected]> Initialize reset_sctlr to 0x00054078 in arm11mpcore_initfn.
Previously, the generic reset mechanism initialized SCTLR to zero because reset_sctlr was not set by the ARM11 MPCore CPU initialization function. The new value follows the fixed-bit requirements documented in ARM DDI 0360F, section 3.4.7, Table 3-20: - Bits [21:16]: 000101, contributing 0x00050000 - Bit [14]: Should Be One / Read As One, contributing 0x00004000 - Bits [6:3]: Should Be One, contributing 0x00000078 V, U, and EE remain clear because their reset values depend on the VINITHI and CFGEND configuration signals. After rebuilding, the test read SCTLR as 0x00054078 instead of zero, and the 0x00050078 mask check passed. Signed-off-by: Felipe Junger <[email protected]> --- target/arm/tcg/cpu32.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index f292a269bf..1999e50290 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -218,6 +218,7 @@ static void arm11mpcore_initfn(Object *obj) cpu->isar.mvfr0 = 0x11111111; cpu->isar.mvfr1 = 0x00000000; cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ + cpu->reset_sctlr = 0x00054078; SET_IDREG(isar, ID_PFR0, 0x111); SET_IDREG(isar, ID_PFR1, 0x1); SET_IDREG(isar, ID_DFR0, 0); -- 2.55.0
