Hello Ali,
On Sat, Aug 29, 2026 at 08:29:48AM +0000, Ali Ahmet Memis wrote:
> From: Ali Ahmet Memiş <[email protected]>
>
> l.extws and l.extwz belong to the ORBIS32 instruction set, but the
> decoder has no entries for them, so they raise an illegal instruction
> exception on every CPU model.
>
> On a 32-bit implementation both are register moves: there is nothing
> above bit 31 to extend into. Implement them as such.
>
> Found while writing an OpenRISC port of Valgrind.
>
> Signed-off-by: Ali Ahmet Memiş <[email protected]>
Thanks, I will queue this.
-Stafford
> ---
> target/or1k/disas.c | 2 ++
> target/or1k/insns.decode | 2 ++
> target/or1k/translate.c | 14 ++++++++++++++
> 3 files changed, 18 insertions(+)
>
> diff --git a/target/or1k/disas.c b/target/or1k/disas.c
> index dc025bd64d..0a46d68d30 100644
> --- a/target/or1k/disas.c
> +++ b/target/or1k/disas.c
> @@ -71,6 +71,8 @@ INSN(exths, "r%d, r%d", a->d, a->a)
> INSN(extbs, "r%d, r%d", a->d, a->a)
> INSN(exthz, "r%d, r%d", a->d, a->a)
> INSN(extbz, "r%d, r%d", a->d, a->a)
> +INSN(extws, "r%d, r%d", a->d, a->a)
> +INSN(extwz, "r%d, r%d", a->d, a->a)
> INSN(cmov, "r%d, r%d, r%d", a->d, a->a, a->b)
> INSN(ff1, "r%d, r%d", a->d, a->a)
> INSN(fl1, "r%d, r%d", a->d, a->a)
> diff --git a/target/or1k/insns.decode b/target/or1k/insns.decode
> index 0d6f7c29f8..cbf8af7f8b 100644
> --- a/target/or1k/insns.decode
> +++ b/target/or1k/insns.decode
> @@ -112,6 +112,8 @@ l_exths 111000 d:5 a:5 ----- - 0000 -- 1100
> l_extbs 111000 d:5 a:5 ----- - 0001 -- 1100
> l_exthz 111000 d:5 a:5 ----- - 0010 -- 1100
> l_extbz 111000 d:5 a:5 ----- - 0011 -- 1100
> +l_extws 111000 d:5 a:5 ----- - 0000 -- 1101
> +l_extwz 111000 d:5 a:5 ----- - 0001 -- 1101
>
> l_add 111000 d:5 a:5 b:5 - 00 ---- 0000
> l_addc 111000 d:5 a:5 b:5 - 00 ---- 0001
> diff --git a/target/or1k/translate.c b/target/or1k/translate.c
> index eb4485312f..e00ef45b9b 100644
> --- a/target/or1k/translate.c
> +++ b/target/or1k/translate.c
> @@ -502,6 +502,20 @@ static bool trans_l_extbz(DisasContext *dc, arg_da *a)
> return true;
> }
>
> +static bool trans_l_extws(DisasContext *dc, arg_da *a)
> +{
> + check_r0_write(dc, a->d);
> + tcg_gen_mov_i32(cpu_R(dc, a->d), cpu_R(dc, a->a));
> + return true;
> +}
> +
> +static bool trans_l_extwz(DisasContext *dc, arg_da *a)
> +{
> + check_r0_write(dc, a->d);
> + tcg_gen_mov_i32(cpu_R(dc, a->d), cpu_R(dc, a->a));
> + return true;
> +}
> +
> static bool trans_l_cmov(DisasContext *dc, arg_dab *a)
> {
> check_r0_write(dc, a->d);
> --
> 2.55.0
>
