On Mon, 7 Sep 2026 17:37:33 +0800
Chen Pei <[email protected]> wrote:
> Populate the DSDT.cxl and CEDT.cxl golden master binaries for the
> RISC-V CXL bios-tables test and empty
> bios-tables-test-allowed-diff.h, following the bios-tables-test update
> process.
>
> The expected AML added by this series is:
>
> DSDT.cxl:
> Device (PC0C) // ACPI0016 CXL host bridge (pxb-cxl, bus 0x0C)
> Name (_CRS, ResourceTemplate () {
> DWordMemory (... 0x40400000 .. 0x405FFFFF ...) // 32-bit MMIO
> QWordMemory (... 0x400100000 .. 0x40010FFFF ...) // 64-bit MMIO
> WordBusNumber (... 0x000C .. 0x000D ...)
> })
> Method (_OSC, ...) // PCI host bridge + CXL UUIDs
> Device (CXLM) // ACPI0017 CXL memory controller
> Name (_HID, "ACPI0017")
> Name (_DEP, Package () { \_SB.PC0C })
> Method (_STA, ...) / Method (_DSM, ...)
>
> CEDT.cxl:
> CHBS : CXL Host Bridge Structure, Register base 0x800000000
> CFMWS: CXL Fixed Memory Window, base 0x810000000, size 4G
>
> Reviewed-by: Junjie Cao <[email protected]>
> Tested-by: Junjie Cao <[email protected]>
> Signed-off-by: Chen Pei <[email protected]>
Reviewed-by: Jonathan Cameron <[email protected]>
