On 9/13/2026 10:14 PM, Richard Henderson wrote:
On 9/7/26 03:14, Daniel Henrique Barboza wrote:
Richard,
This tlb_flush change is giving a +20% performance boost in riscv64- tuxrun.
From
this:
23/23 func-thorough+func-riscv64-thorough+thorough - qemu:func-riscv64- tuxrun
OK 92.71s 4 subtests passed
To this:
23/23 func-thorough+func-riscv64-thorough+thorough - qemu:func-riscv64- tuxrun
OK 73.45s 4 subtests passed
Other tests weren't that affected - I take it has to do with the amount of
sfence.vma being issued. They look fine in my own testing with an emulated
Ubuntu host as well.
This is all fantastic but I wonder if we're missing something. If you could
please take a look at these 2 patches and see if we're handling the tlb flushes
according that would be terrific.
It looks good.
The only possible improvement would be to avoid flushing the PRV_M 1-1 tlb,
using tlb_flush_by_mmuidx / tlb_flush_page_by_mmuidx.
You could also rename MMUIdx_M to MMUIdx_PHYS and use it in modes other than
PRV_M when the mmu is disabled, simplifying the test at the start of
get_physical_address.
Thanks for having a look! I believe we have a potential cleanup to do based on
what you said in patch 1. Probably follow-up material since it'll be a bit
too much in the context handled here.
Cheers,
Daniel
r~
