Implement packed horizontal reduction-sum operations. Cover signed and unsigned variants for byte, halfword, and word elements. These instructions sum all packed elements in rs1 and add the result to rs2. Add the associated decode entries, translators and helpers.
Signed-off-by: Molly Chen <[email protected]> --- target/riscv/helper.h | 8 ++++++++ target/riscv/insn32.decode | 8 ++++++++ target/riscv/tcg/insn_trans/trans_rvp.c.inc | 8 ++++++++ target/riscv/tcg/psimd_helper.c | 15 +++++++++++++++ 4 files changed, 39 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index cca3b88535d..824779f05d0 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1511,3 +1511,11 @@ DEF_HELPER_3(psas_wx, i64, env, i64, i64) DEF_HELPER_3(pssa_wx, i64, env, i64, i64) DEF_HELPER_3(paas_wx, i64, env, i64, i64) DEF_HELPER_3(pasa_wx, i64, env, i64, i64) + +/* Packed SIMD - Horizontal Reduction Operations */ +DEF_HELPER_3(predsum_bs, tl, env, tl, tl) +DEF_HELPER_3(predsumu_bs, tl, env, tl, tl) +DEF_HELPER_3(predsum_hs, tl, env, tl, tl) +DEF_HELPER_3(predsumu_hs, tl, env, tl, tl) +DEF_HELPER_3(predsum_ws, i64, env, i64, i64) +DEF_HELPER_3(predsumu_ws, i64, env, i64, i64) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 3cfd8602c1c..3f8314d382b 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -1290,3 +1290,11 @@ psas_wx 1001001 ..... ..... 110 ..... 0111011 @r pssa_wx 1001011 ..... ..... 110 ..... 0111011 @r paas_wx 1001101 ..... ..... 110 ..... 0111011 @r pasa_wx 1001111 ..... ..... 110 ..... 0111011 @r + +# Packed SIMD - Horizontal Reduction Operations +predsum_bs 1001110 ..... ..... 100 ..... 0011011 @r +predsumu_bs 1011110 ..... ..... 100 ..... 0011011 @r +predsum_hs 1001100 ..... ..... 100 ..... 0011011 @r +predsumu_hs 1011100 ..... ..... 100 ..... 0011011 @r +predsum_ws 1001101 ..... ..... 100 ..... 0011011 @r +predsumu_ws 1011101 ..... ..... 100 ..... 0011011 @r diff --git a/target/riscv/tcg/insn_trans/trans_rvp.c.inc b/target/riscv/tcg/insn_trans/trans_rvp.c.inc index c991ac37e32..726707b2956 100644 --- a/target/riscv/tcg/insn_trans/trans_rvp.c.inc +++ b/target/riscv/tcg/insn_trans/trans_rvp.c.inc @@ -664,3 +664,11 @@ GEN_SIMD_TRANS_64_VXSAT(psas_wx) GEN_SIMD_TRANS_64_VXSAT(pssa_wx) GEN_SIMD_TRANS_64(paas_wx) GEN_SIMD_TRANS_64(pasa_wx) + +/* Packed SIMD - Horizontal Reduction Operations */ +GEN_SIMD_TRANS(predsum_bs) +GEN_SIMD_TRANS(predsumu_bs) +GEN_SIMD_TRANS(predsum_hs) +GEN_SIMD_TRANS(predsumu_hs) +GEN_SIMD_TRANS_64(predsum_ws) +GEN_SIMD_TRANS_64(predsumu_ws) diff --git a/target/riscv/tcg/psimd_helper.c b/target/riscv/tcg/psimd_helper.c index 0cb81151d79..397efa66aeb 100644 --- a/target/riscv/tcg/psimd_helper.c +++ b/target/riscv/tcg/psimd_helper.c @@ -2462,3 +2462,18 @@ GEN_PSIMD_XPAIR_AVG_BINOP(paas_wx, uint64_t, int32_t, int64_t, GEN_PSIMD_XPAIR_AVG_BINOP(pasa_wx, uint64_t, int32_t, int64_t, EXTRACT32, INSERT32, ELEMS_W, PSIMD_DO_ADD, PSIMD_DO_SUB) + +/* Horizontal sum operations */ + +GEN_PSIMD_REDSUM(predsum_bs, target_ulong, int64_t, int8_t, + EXTRACT8, ELEMS_B, (int64_t)(int32_t)rs2) +GEN_PSIMD_REDSUM(predsumu_bs, target_ulong, uint64_t, uint8_t, + EXTRACT8, ELEMS_B, rs2) +GEN_PSIMD_REDSUM(predsum_hs, target_ulong, int64_t, int16_t, + EXTRACT16, ELEMS_H, (int64_t)(int32_t)rs2) +GEN_PSIMD_REDSUM(predsumu_hs, target_ulong, uint64_t, uint16_t, + EXTRACT16, ELEMS_H, rs2) +GEN_PSIMD_REDSUM(predsum_ws, uint64_t, int64_t, int32_t, + EXTRACT32, ELEMS_W, (int64_t)rs2) +GEN_PSIMD_REDSUM(predsumu_ws, uint64_t, uint64_t, uint32_t, + EXTRACT32, ELEMS_W, rs2) -- 2.34.1
