From: Peter Maydell <[email protected]> The "hint space" is a region of the encoding space which is defined to NOP if not specified as an architected instruction, so that future instructions can be added there which fall back to NOPs on older CPUs. In the A32 encoding, this hint space was carved out of the MSR (imm) insn by using the fact that a field_mask (bits [19:15]) of 0b0000 meant that an MSR (imm) would set no parts of the CPSR from the immediate, so it was always NOP on existing CPUs.
For the T1 encoding, the hint space is in a range that used to UNDEF in Armv5, and so the hint insns and the NOP region must all UNDEF before v6T2. Rather than putting this check in the trans functions for each hint insn and for the NOP space (which is a lot of places, and awkward since those trans functions are often shared with the A64 and A32 encodings), put in a decode line that covers the whole space which we check before any of the hints and which will explicitly UNDEF if necessary. Cc: [email protected] Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/4208 Signed-off-by: Peter Maydell <[email protected]> Reviewed-by: Richard Henderson <[email protected]> Message-id: [email protected] (cherry picked from commit 2931a675e9d3fcddedf673509fe9759955fc616d) Signed-off-by: Michael Tokarev <[email protected]> diff --git a/target/arm/tcg/t16.decode b/target/arm/tcg/t16.decode index 646c74929d5..cbc99534f8f 100644 --- a/target/arm/tcg/t16.decode +++ b/target/arm/tcg/t16.decode @@ -224,6 +224,9 @@ REVSH 1011 1010 11 ... ... @rdm { { + # Before v6T2 this was not NOP space and must UNDEF + MAYBE_UNDEF_T1_HINT 1011 1111 ---- 0000 + YIELD 1011 1111 0001 0000 WFE 1011 1111 0010 0000 WFI 1011 1111 0011 0000 diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 7097077880e..d6dbbf48a7f 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -4547,6 +4547,24 @@ static bool trans_NOP(DisasContext *s, arg_NOP *a) return true; } +static bool trans_MAYBE_UNDEF_T1_HINT(DisasContext *s, + arg_MAYBE_UNDEF_T1_HINT *a) +{ + /* + * The Thumb T1 encoding hint space was only defined starting + * in v6T2 for A-profile. For M-profile it always exists, even + * in v6M. + */ + if (arm_dc_feature(s, ARM_FEATURE_M) || + arm_dc_feature(s, ARM_FEATURE_THUMB2)) { + /* Allow decode to fall through to the hint insns and NOP space */ + return false; + } + /* On the earlier cores, we must UNDEF */ + unallocated_encoding(s); + return true; +} + static bool trans_MSR_imm(DisasContext *s, arg_MSR_imm *a) { uint32_t val = ror32(a->imm, a->rot * 2); -- 2.47.3
