Signed-off-by: Molly Chen <[email protected]>
Reviewed-by: Chao Liu <[email protected]>
---
target/riscv/tcg/insn_trans/trans_rvb.c.inc | 4 +++-
target/riscv/tcg/insn_trans/trans_rvp.c.inc | 2 +-
target/riscv/tcg/tcg-cpu.c | 6 ++----
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/riscv/tcg/insn_trans/trans_rvb.c.inc
b/target/riscv/tcg/insn_trans/trans_rvb.c.inc
index 3e74be223b0..48bc5df0378 100644
--- a/target/riscv/tcg/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/tcg/insn_trans/trans_rvb.c.inc
@@ -527,7 +527,9 @@ static bool trans_brev8(DisasContext *ctx, arg_brev8 *a)
static bool trans_pack(DisasContext *ctx, arg_pack *a)
{
- REQUIRE_ZBKB(ctx);
+ if (!has_ext(ctx, RVP) && !ctx->cfg_ptr->ext_zbkb) {
+ return false;
+ }
return gen_arith(ctx, a, EXT_NONE, gen_pack, NULL);
}
diff --git a/target/riscv/tcg/insn_trans/trans_rvp.c.inc
b/target/riscv/tcg/insn_trans/trans_rvp.c.inc
index bec44e98f7c..8c8c6ba3a6f 100644
--- a/target/riscv/tcg/insn_trans/trans_rvp.c.inc
+++ b/target/riscv/tcg/insn_trans/trans_rvp.c.inc
@@ -1436,4 +1436,4 @@ GEN_DWS_REG_OP(psll_dws, EXT_NONE, true, tcg_gen_shl_tl)
GEN_DWS_REG_OP(psrl_dws, EXT_ZERO, true, tcg_gen_shr_tl)
GEN_DWS_REG_OP(psra_dws, EXT_SIGN, true, tcg_gen_sar_tl)
-GEN_DW_PAIR_ARITH(ppaire_dh, REQUIRE_ZBKB(ctx); , EXT_NONE, gen_pack)
+GEN_DW_PAIR_ARITH(ppaire_dh, , EXT_NONE, gen_pack)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 3e72e2ffd7f..4d57192d1e1 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -562,10 +562,8 @@ static void riscv_cpu_validate_p(RISCVCPU *cpu, Error
**errp)
return;
}
- if (!(cpu->cfg.ext_zmmul && cpu->cfg.ext_zba && cpu->cfg.ext_zbb &&
- cpu->cfg.ext_zbkb)) {
- error_setg(errp, "P extension requires zmmul, zba, zbb and zbkb "
- "extensions");
+ if (!(cpu->cfg.ext_zmmul && cpu->cfg.ext_zba && cpu->cfg.ext_zbb)) {
+ error_setg(errp, "P extension requires zmmul, zba and zbb extensions");
return;
}
}
--
2.34.1