With vtype uninitialized, VILL might be set, leading to SIGILL. Also, assert vtype initialized for whole-register stores and moves.
Cc: Palmer Dabbelt <[email protected]> Reported-by: Max Chou <[email protected]> Signed-off-by: Richard Henderson <[email protected]> --- tcg/riscv64/tcg-target.c.inc | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/tcg/riscv64/tcg-target.c.inc b/tcg/riscv64/tcg-target.c.inc index 2ce9d47a633..de9a3570b23 100644 --- a/tcg/riscv64/tcg-target.c.inc +++ b/tcg/riscv64/tcg-target.c.inc @@ -775,6 +775,7 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) case TCG_TYPE_V64: case TCG_TYPE_V128: case TCG_TYPE_V256: + tcg_debug_assert(s->riscv_cur_type != TCG_TYPE_COUNT); { int lmul = type - riscv_lg2_vlenb; int nf = 1 << MAX(lmul, 0); @@ -1014,6 +1015,10 @@ static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, unsigned idx = type - riscv_lg2_vlenb; tcg_debug_assert(idx < ARRAY_SIZE(whole_reg_ld)); + /* We must initialize vtype to something to avoid VILL. */ + if (s->riscv_cur_type == TCG_TYPE_COUNT) { + set_vtype(s, type, MO_8); + } insn = whole_reg_ld[idx]; } else { static const RISCVInsn unit_stride_ld[] = { @@ -1046,6 +1051,7 @@ static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, case TCG_TYPE_V64: case TCG_TYPE_V128: case TCG_TYPE_V256: + tcg_debug_assert(s->riscv_cur_type != TCG_TYPE_COUNT); if (type >= riscv_lg2_vlenb) { static const RISCVInsn whole_reg_st[] = { OPC_VS1R_V, OPC_VS2R_V, OPC_VS4R_V, OPC_VS8R_V -- 2.53.0
