On 2026/09/21 14:59, Clément MATHIEU--DRIF wrote:
The SR-IOV PCIe capability exposes 6 regions (no ROM), each with a dedicated 32-bit configuration field. Fix the reset loop to write 32 bits instead of 64 bits and stop after PCI_SRIOV_NUM_BARS iterations.As a side effect of this change, update PCIESriovPF::vf_bar_type to match the number of regions exposed by SR-IOV and rework the associated assert statements. Fixes: c8bc4db403e1 ("pcie_sriov: Reset SR-IOV extended capability") Signed-off-by: Clement Mathieu--Drif <[email protected]>
Reviewed-by: Akihiko Odaki <[email protected]>
