Am 20. September 2026 11:54:48 UTC schrieb Gaurav Sharma
<[email protected]>:
Hi Gaurav,
>Changes in v1:
>
>This series adds Asymmetric Multiprocessing (AMP) boot support for
>the Cortex-M7 core on the i.MX8MP SoC. The M7 firmware can be loaded
>and started from Linux running on the Cortex-A53 cores via the
>remoteproc framework.
>
>The series introduces the following peripheral models needed for AMP:
> - GPC (General Power Controller)
> - GPR (General Purpose Registers)
> - SRC (System Reset Controller) authored by Bernhard Beschow
> <[email protected]>
> - MU (Messaging Unit)
> - Extends the CCM with M7 clock outputs and wires into the i.MX8MP SoC
> - Enable Cortex-M7 boot in i.MX8MP EVK functional test
>
>Changes in v2:
>
>- Removed the usage of device_class_set_legacy_reset in imx8mp gpc,gpr,mu and
> src.
>- Removed the usage of 'smp' , 'maxcpus' and 'enable-cm7' to make the
> invocation simpler.
>- Cleaned up imx8mp_src by removing redundant/unused code.
>- Updated Maintainers and improved the imx8mp documentation
>
>Changes in v3:
>
>- Added a new patch for smp removal from test_imx8mp_evk.py.
>- Added a new patch to introduce IRQ splitting for i.MX8MP AMP interrupt
> routing.
>- Added a new patch to rename FSL_IMX8MP_NUM_CPUS to FSL_IMX8MP_NUM_A53,
> since M7 is being introduced now.
>- In GPR, parent_phases moved from global variable to class struct
>- M7 reset handling moved from the machine to SRC device model.
>- Added ITCM and DTCM memory regions to support zephyr firmware loading.
>
>Signed-off-by: Gaurav Sharma <[email protected]>
>
>Bernhard Beschow (1):
> hw/misc: Add SRC (System Reset Controller) to i.MX8MP
I think you can claim ownership of the SRC since I think only non-copyrightable
changes are left from the original commit.
>
>Gaurav Sharma (9):
> hw/misc: Add i.MX8MP GPC (General Power Controller) IP
> hw/misc: Add GPR (General Purpose Register) IP to iMX8MP
> hw/misc: Add MU (Messaging Unit) IP to i.MX8MP device model
> hw/misc: Extend i.MX8MP CCM with Cortex-M7 clock outputs
> hw/arm: Enable Cortex-M7 AMP boot on i.MX8MP
This should be the last patch of the series. The paches below are refactorings
and should rather be the first patches in the series. Right now they depend on
changes in this series which prevents them from being cherry-picked for early
merge.
Generally, touching the same code twice in a series is discuraged and should
only be done with good reasons. In favor of a clean history QEMU is not
interested in the detours during development and instead we pretend as if we
knew the shortest path towards a goal in the first place. Makes sense?
Best regards,
Bernhard
> hw/arm: Rename FSL_IMX8MP_NUM_CPUS to FSL_IMX8MP_NUM_A53
> MAINTAINERS: Merge MCIMX8MM-EVK and MCIMX8MP-EVK entries
> hw/arm: Add IRQ splitter for i.MX8MP AMP interrupt routing
> tests/functional: Fix i.MX8MP EVK SMP configuration
>
> MAINTAINERS | 13 +-
> docs/system/arm/imx8m.rst | 188 ++++++++-
> hw/arm/Kconfig | 4 +
> hw/arm/fsl-imx8mp.c | 227 +++++++++--
> hw/arm/imx8mp-evk.c | 5 +-
> hw/misc/Kconfig | 12 +
> hw/misc/imx8mp_ccm.c | 9 +
> hw/misc/imx8mp_gpc.c | 146 +++++++
> hw/misc/imx8mp_gpr.c | 155 ++++++++
> hw/misc/imx8mp_mu.c | 328 ++++++++++++++++
> hw/misc/imx8mp_src.c | 411 ++++++++++++++++++++
> hw/misc/meson.build | 4 +
> hw/misc/trace-events | 5 +
> include/hw/arm/fsl-imx8mp.h | 33 +-
> include/hw/misc/imx8mp_ccm.h | 3 +
> include/hw/misc/imx8mp_gpc.h | 34 ++
> include/hw/misc/imx8mp_gpr.h | 62 +++
> include/hw/misc/imx8mp_mu.h | 53 +++
> include/hw/misc/imx8mp_src.h | 52 +++
> tests/functional/aarch64/test_imx8mp_evk.py | 1 -
> 20 files changed, 1696 insertions(+), 49 deletions(-)
> create mode 100644 hw/misc/imx8mp_gpc.c
> create mode 100644 hw/misc/imx8mp_gpr.c
> create mode 100644 hw/misc/imx8mp_mu.c
> create mode 100644 hw/misc/imx8mp_src.c
> create mode 100644 include/hw/misc/imx8mp_gpc.h
> create mode 100644 include/hw/misc/imx8mp_gpr.h
> create mode 100644 include/hw/misc/imx8mp_mu.h
> create mode 100644 include/hw/misc/imx8mp_src.h
>
