UDC_ISR.EP_POOL_ACK says that at least one endpoint in UDC_EP_ACK_ISR has an ack. It is read only, so a write cannot clear it.
Clear it when bits 3:0 of UDC_EP_ACK_ISR are all 0, which means no programmable endpoint has an ack. Signed-off-by: Jamin Lin <[email protected]> --- hw/usb/aspeed-udc.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/hw/usb/aspeed-udc.c b/hw/usb/aspeed-udc.c index 95fe823534..bdbd1a78b8 100644 --- a/hw/usb/aspeed-udc.c +++ b/hw/usb/aspeed-udc.c @@ -335,6 +335,13 @@ static void aspeed_udc_write(void *opaque, hwaddr offset, uint64_t data, aspeed_udc_update_irq(s); break; case R_UDC_EP_ACK_ISR: + val &= 0x0000000f; + s->regs[reg] &= ~val; + if (!s->regs[R_UDC_EP_ACK_ISR]) { + s->regs[R_UDC_ISR] &= ~R_UDC_ISR_EP_POOL_ACK_MASK; + } + aspeed_udc_update_irq(s); + break; case R_UDC_EP_NAK_ISR: val &= 0x0000000f; s->regs[reg] &= ~val; -- 2.53.0
