The AMX tiles feature uses a larger than 4kB area in xsave. This fix removes the code that disables AMX tiles in the partition and it adjusts the supported CPUID to advertise AMX tiles.
Signed-off-by: Doru Blânzeanu <[email protected]> --- accel/mshv/mshv-all.c | 18 +++++------------- target/i386/mshv/mshv-cpu.c | 16 ---------------- 2 files changed, 5 insertions(+), 29 deletions(-) diff --git a/accel/mshv/mshv-all.c b/accel/mshv/mshv-all.c index 725ccd0511..99b2b3362a 100644 --- a/accel/mshv/mshv-all.c +++ b/accel/mshv/mshv-all.c @@ -187,7 +187,6 @@ static int create_partition(int mshv_fd, int *vm_fd) { int ret; uint64_t pt_flags, host_proc_features; - union hv_partition_processor_xsave_features disabled_xsave_features; union hv_partition_processor_features disabled_partition_features = {0}; struct mshv_create_partition_v2 args = {0}; @@ -200,17 +199,6 @@ static int create_partition(int mshv_fd, int *vm_fd) (1ULL << MSHV_PT_BIT_GPA_SUPER_PAGES) | (1ULL << MSHV_PT_BIT_CPU_AND_XSAVE_FEATURES); - /* enable all */ - disabled_xsave_features.as_uint64 = 0; - /* - * AMX TILE XSAVE state (XTILE_DATA) is 8KB, which exceeds the - * current fixed 4KB XSAVE buffer size. - */ - disabled_xsave_features.amx_tile_support = 1; - disabled_xsave_features.amx_bf16_support = 1; - disabled_xsave_features.amx_int8_support = 1; - disabled_xsave_features.amx_fp16_support = 1; - /* * query host for supported processor features and disable unsupported * features: (0 means supported, 1 means disabled, hence the negation) @@ -238,10 +226,14 @@ static int create_partition(int mshv_fd, int *vm_fd) args.pt_cpu_fbanks[0] |= disabled_partition_features.as_uint64[0]; args.pt_cpu_fbanks[1] |= disabled_partition_features.as_uint64[1]; + /* + * for now, all the xsave features are enabled, the filtering is only done + * at the CPUID level + * TODO: filter the xsave features based on the CPUID derived from Cpu model + */ /* populate args structure */ args.pt_flags = pt_flags; args.pt_isolation = MSHV_PT_ISOLATION_NONE; - args.pt_disabled_xsave = disabled_xsave_features.as_uint64; args.pt_num_cpu_fbanks = MSHV_NUM_CPU_FEATURES_BANKS; ret = ioctl(mshv_fd, MSHV_CREATE_PARTITION, &args); diff --git a/target/i386/mshv/mshv-cpu.c b/target/i386/mshv/mshv-cpu.c index 5b845b3e4e..21a3534578 100644 --- a/target/i386/mshv/mshv-cpu.c +++ b/target/i386/mshv/mshv-cpu.c @@ -2234,22 +2234,6 @@ uint32_t mshv_get_supported_cpuid(uint32_t func, uint32_t idx, int reg) */ ret &= ~CPUID_7_0_ECX_LA57; } - if (func == 0x07 && idx == 0 && reg == R_EDX) { - /* - * AMX TILE XSAVE state (XTILE_DATA) is 8KB, which exceeds the - * current fixed 4KB XSAVE buffer size. Filter until buffer - * sizing is computed dynamically from CPUID. - */ - ret &= ~CPUID_7_0_EDX_AMX_TILE; - ret &= ~CPUID_7_0_EDX_AMX_BF16; - ret &= ~CPUID_7_0_EDX_AMX_INT8; - } - if (func == 0x07 && idx == 1 && reg == R_EAX) { - ret &= ~CPUID_7_1_EAX_AMX_FP16; - } - if (func == 0x07 && idx == 1 && reg == R_EDX) { - ret &= ~CPUID_7_1_EDX_AMX_COMPLEX; - } return ret; } -- 2.53.0
