> On 16 Sep 2026, at 8:15 PM, Eric Auger <[email protected]> wrote:
>
> !-------------------------------------------------------------------|
> CAUTION: External Email
>
> |-------------------------------------------------------------------!
>
> From: Shaju Abraham <[email protected]>
>
> Include cpu-idregs.h.inc multiple times with different definitions for the
> X-macros. This will generate tables for all Arm64 ID registers and their
> fields. Additionally, initialize the tables with all architecturally defined
> values. These tables will be consumed by the property layer in future
> patches.
>
> Note:
> This triggers a minot checkpatch error but I prefer to keep the coma in
> the macro.
> ERROR: Macros with complex values should be enclosed in parenthesis
> +#define IDREG_FIELD_ARCH_VAL(v) (v),
>
> Co-authored-by: Khushit Shah <[email protected]>
> Signed-off-by: Khushit Shah <[email protected]>
> Signed-off-by: Shaju Abraham <[email protected]>
> Signed-off-by: Eric Auger <[email protected]>
>
LGTM, only minor nits.
> ---
> v7 -> v8
> Adaptation after removal of struct ArmIdRegArchVal
>
> v5 -> v6
> - restored support of enum values
> ---
> target/arm/cpu-idregs.c | 96 +++++++++++++++++++++++++++++++++++++++++
> target/arm/meson.build | 1 +
> 2 files changed, 97 insertions(+)
> create mode 100644 target/arm/cpu-idregs.c
>
> diff --git a/target/arm/cpu-idregs.c b/target/arm/cpu-idregs.c
> new file mode 100644
> index 0000000000..199d593153
> --- /dev/null
> +++ b/target/arm/cpu-idregs.c
> @@ -0,0 +1,96 @@
> +/*
> + * ARM ID register field table.
> + *
> + * Builds the per-id-register field descriptor arrays and the global
> + * arm_idregs[] table.
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +#include "qemu/osdep.h"
> +#include "qemu/error-report.h"
> +#include "qapi/error.h"
> +#include "cpu.h"
> +#include "cpu-idregs.h"
> +
> +/*
> + * Generate an array of architecturely defined values for each field
> + * associated with enum values
> + */
> +
> +#define IDREG_START(reg)
> +#define IDREG_END(reg)
> +#define IDREG_FIELD(reg, field, shift, length)
> +#define IDREG_FIELD_START(reg, field, shift, length) \
> + static const uint64_t reg##_##field##_arch_vals[] = {
> +#define IDREG_FIELD_ARCH_VAL(v) (v),
> +#define IDREG_FIELD_END(reg, field) \
> + };
> +
> +#include "cpu-idregs.h.inc"
> +
> +#undef IDREG_START
> +#undef IDREG_END
> +#undef IDREG_FIELD
> +#undef IDREG_FIELD_START
> +#undef IDREG_FIELD_END
> +#undef IDREG_FIELD_ARCH_VAL
> +
> +/* generate an array of per-register ArmIdRegField[] descriptors */
> +
> +#define IDREG_START(reg) \
> + static ARM64SysRegField reg##_fields[] = {
> +
> +#define IDREG_END(reg) \
> + };
> +
> +#define IDREG_FIELD_START(reg, field, _shift, _length) \
> + { \
Some \ are tabbed, and others are not.
> + .name = #field, \
> + .index = reg##_IDX, \
> + .shift = (_shift), \
> + .length = (_length), \
> + .arch_vals = (uint64_t *)reg##_##field##_arch_vals, \
> + .arch_vals_count = ARRAY_SIZE(reg##_##field##_arch_vals), \
> + },
> +
> +#define IDREG_FIELD(reg, field, _shift, _length) \
> + { \
> + .name = #field, \
> + .index = reg##_IDX, \
> + .shift = (_shift), \
> + .length = (_length), \
> + },
> +
> +#define IDREG_FIELD_ARCH_VAL(v)
> +
> +#define IDREG_FIELD_END(reg, field)
> +
> +#include "cpu-idregs.h.inc"
> +
> +#undef IDREG_START
> +#undef IDREG_END
> +#undef IDREG_FIELD
> +#undef IDREG_FIELD_START
> +#undef IDREG_FIELD_END
> +#undef IDREG_FIELD_ARCH_VAL
> +
> +/* generate an array of top level ID registers */
> +
> +#define IDREG_END(reg)
> +#define IDREG_FIELD(reg, field, shift, length)
> +#define IDREG_FIELD_START(reg, field, shift, length)
> +#define IDREG_FIELD_ARCH_VAL(v)
> +#define IDREG_FIELD_END(reg, field)
> +
> +#define IDREG_START(reg) \
> + [reg##_IDX] = { \
> + .name = #reg, \
> + .index = reg##_IDX, \
> + .fields = reg##_fields, \
> + .fields_count = ARRAY_SIZE(reg##_fields), \
.writable_mask = 0ULL, \?
> + },
> +
> +ARM64SysReg arm64_id_regs[NUM_ID_IDX] = {
> +#include "cpu-idregs.h.inc"
> +};
> +
> diff --git a/target/arm/meson.build b/target/arm/meson.build
> index 0369f96b4c..384d90c530 100644
> --- a/target/arm/meson.build
> +++ b/target/arm/meson.build
> @@ -30,6 +30,7 @@ arm_common_user_system_ss.add(when: 'TARGET_AARCH64',
> if_true: files(
>
> arm_common_system_ss.add(files(
> 'arm-qmp-cmds.c',
> + 'cpu-idregs.c',
> ))
> arm_system_ss.add(when: 'CONFIG_KVM', if_true: files('hyp_gdbstub.c',
> 'kvm.c'))
> arm_system_ss.add(when: 'CONFIG_HVF', if_true: files('hyp_gdbstub.c'))
> --
> 2.53.0
>
