Hi and quick ping if you could take a look at the series. Thanks, Dan.
On Fri, Sep 18, 2026 at 8:11 AM Purr Box <[email protected]> wrote: > Thank you very much in advance! I'm looking forward to getting sun3 > supported. > > Dan. > > On Fri, Sep 18, 2026 at 6:32 AM Mark Cave-Ayland < > [email protected]> wrote: > >> On 09/09/2026 19:54, Purr Box wrote: >> >> > Gentle ping on this series. v5 addresses Zoltan's review feedback from >> v4 (fsave >> > simplification, NMI edge-trigger rationale, added Signed-off-by). Would >> appreciate >> > any review when you have a chance. >> >> Apologies for the delay: I will have quick look through the series over >> the next few >> days, although I suspect I'd need to defer to Laurent's greater 68k >> knowledge here. >> >> > Dan. >> > >> > On Wed, Sep 2, 2026 at 9:46 PM 54weasels <[email protected] >> > <mailto:[email protected]>> wrote: >> > >> > This series adds M68020/030-specific features to the m68k target >> that >> > are required by the Sun-3 machine (series C) and its PROM/SunOS >> guests: >> > >> > 1/6: CAAR register stub for 68020/030 cache control >> > 2/6: fsave/frestore fix for 68881 (non-68040) FPU frames >> > 3/6: Edge-triggered NMI semantics for Level 7 interrupts >> > 4/6: Function code extraction during TLB fills >> > 5/6: Custom MMU intercept hook for Sun-3 transparent translation >> > 6/6: Physical Bus Error and M68020 Format 0xB stack frames >> > >> > Changes since v4: >> > - Added Signed-off-by to all patches. >> > - Patch 2/6 (fsave): Addressed Zoltan's review — replaced >> redundant >> > M68040||FPU check with just M68K_FEATURE_FPU, removed >> unnecessary >> > if/else in frestore, moved Context: below --- separator. >> > - Patch 3/6 (NMI): Addressed Zoltan's review — nmi_pending >> cannot be >> > replaced by testing pending_level == 7. The flag captures the >> edge >> > transition (level < 7 → 7) required by Motorola's NMI >> specification, >> > while pending_level only reflects the current interrupt level. >> > Testing pending_level alone would produce level-triggered >> behavior, >> > firing on every interrupt check rather than once per edge. >> > - Rebased on current master. >> > >> > 54weasels (6): >> > target/m68k: Add dummy CAAR register >> > target/m68k: Fix fsave/frestore for 68881 FPU >> > target/m68k: Fix NMI pending for Level 7 interrupts >> > target/m68k: Extract Function Codes during TLB fills >> > target/m68k: Implement custom MMU intercept hook >> > target/m68k: Implement Physical Bus Error and Stack >> > >> > target/m68k/cpu.c | 4 +- >> > target/m68k/cpu.h | 21 ++++- >> > target/m68k/helper.c | 130 ++++++++++++++++++++++++++++- >> > target/m68k/op_helper.c | 175 >> ++++++++++++++++++++++++++-------------- >> > target/m68k/translate.c | 30 ++++--- >> > 5 files changed, 280 insertions(+), 80 deletions(-) >> > >> > -- >> > 2.50.1 (Apple Git-155) >> >> >> ATB, >> >> Mark. >> >>
