[PATCH 01/10] target/hexagon: Allow temporary HVX write and future write

[Brian Cain]

HVX packets with Vx.tmp/Vx reg writes were incorrectly rejected.

Cc: Taylor Simpson <ltaylorsimp...@gmail.com>
Signed-off-by: Brian Cain <brian.c...@oss.qualcomm.com>
---
 target/hexagon/translate.h | 13 ++++++-------
 1 file changed, 6 insertions(+), 7 deletions(-)

diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h
index e17261761b2..7bc6207a08c 100644
--- a/target/hexagon/translate.h
+++ b/target/hexagon/translate.h
@@ -237,12 +237,13 @@ static inline void ctx_log_vreg_write(DisasContext *ctx,
             ctx->has_hvx_overlap = true;
         }
     }
-    if (!test_bit(rnum, ctx->vregs_written)) {
-        set_bit(rnum, ctx->vregs_written);
-    } else {
-        set_bit(rnum, ctx->vregs_multi_write);
-    }
+
     if (type != EXT_TMP) {
+        if (!test_bit(rnum, ctx->vregs_written)) {
+            set_bit(rnum, ctx->vregs_written);
+        } else {
+            set_bit(rnum, ctx->vregs_multi_write);
+        }
         if (!test_bit(rnum, ctx->vregs_updated)) {
             ctx->vreg_log[ctx->vreg_log_idx] = rnum;
             ctx->vreg_log_idx++;
@@ -263,8 +264,6 @@ static inline void ctx_log_vreg_write(DisasContext *ctx,
         set_bit(rnum, ctx->vregs_updated_tmp);
         if (is_predicated) {
             set_bit(rnum, ctx->predicated_tmp_vregs);
-        } else {
-            set_bit(rnum, ctx->vregs_uncond);
         }
     }
 }
-- 
2.34.1